Speculation: Ryzen 4000 series/Zen 3

[moinmoin]

Which one is the premium $$$ cpu, the 4800u or the 4800h model?

Of those two 4800U would be the more premium model, since 4800H is surpassed by 4800HS already.

 

[Richie Rich]

Richie, if you're so sure about SMT4 being a part of Zen 3, would you be willing to eat a can of cat food if Zen 3 ends up NOT having SMT4? It's only tradition around these parts of town...

How much are you sure about SMT4 not being in Zen3?
Are you sure for 99.9% against mine 0.1%? That's the ratio of 1 000 : 1.
When I bet 10$ are you going to give 10,000$ when Zen3 will have SMT4?

How about that? Are you still so confident? Or would you like lower ratio?


There is too big silence about Zen3 now. This silence indirectly confirms early Norrod's words about completely new architecture. And now what a coincidence, SMT is disabled, and the reason is broken SMT even after several metal re-spins and needs new full revision. How many people believes that?

 

[Shivansps]

But to be honest, the feeling I'm getting here is the APU isn't horribly memory bottlenecked, even with 8CUs clocked at 1850mhz. Not in Fire Strike at least, though Time Spy pushes your memory config harder, so will be better to really put the memory subsystem to the test.

Well, yeah, 128bit LPDDR4X-4266... Vega 8 @ 1750mhz also works very well with 128bit DDR4-3200... This is why there was no technical need to reduce the size of the IGP and it was more of a "we are already beating the crap out of Intel igps, there is no need for more" case.

 

[Glo.]

How much are you sure about SMT4 not being in Zen3?
Are you sure for 99.9% against mine 0.1%? That's the ratio of 1 000 : 1.
When I bet 10$ are you going to give 10,000$ when Zen3 will have SMT4?

How about that? Are you still so confident? Or would you like lower ratio?


There is too big silence about Zen3 now. This silence indirectly confirms early Norrod's words about completely new architecture. And now what a coincidence, SMT is disabled, and the reason is broken SMT even after several metal re-spins and needs new full revision. How many people believes that?

It appears that ONLY YOU believe that Zen 3 is SMT4, even when you have clues that its not the case, and that good, realiable sources said it is only SMT2.

Are YOU willing to pay me 10000$ if Zen 3 is SMT2, only? Because that is the easiest bet to win, for me.

 

[RetroZombie]

It appears that ONLY YOU believe that Zen 3 is SMT4

I also believe in SMT4, but only if amd would do a different zen3 for server vs desktop.
But why bother? They don't have enough resources and it's easier just to increase the number of chiplets if more threads are needed.
So i do believe but also don't believe

 

[Richie Rich]

It appears that ONLY YOU believe that Zen 3 is SMT4, even when you have clues that its not the case, and that good, realiable sources said it is only SMT2.

Are YOU willing to pay me 10000$ if Zen 3 is SMT2, only? Because that is the easiest bet to win, for me.

I've never said I'm 99.9% sure about SMT4 so I cannot accept your bet. I admit the probability for SMT4 is very low around 0.1%. So do you accept bet of my 10$ vs. yours 10,000$?

You guys are so sure about no SMT4 so do not hesitate and take the easiest 10$ in your life
So you, Saylick... and somebody else would like to join?

I also believe in SMT4, but only if amd would do a different zen3 for server vs desktop.
But why bother? They don't have enough resources and it's easier just to increase the number of chiplets if more threads are needed.
So i do believe but also don't believe

Why they would have different Zen3 for desktop? You can disable SMT in BIOS or possiby reduce it to SMT2.

 

[amrnuke]

I admit the probability for SMT4 is very low around 0.1%.

That is NOT what you have been saying all along.

 

[RetroZombie]

Why they would have different Zen3 for desktop? You can disable SMT in BIOS or possiby reduce it to SMT2.

It would not only be SMT4 in a server specific chiplet, bigger L2/L3 caches, chiplet aggregate capability, addon coprocessors/accelerators, ...
The desktop version all that would be cut.

 

[uzzi38]

That is NOT what you have been saying all along.

He hath seen the light... and has decided to backtrack as soon as possible.

 

[Saylick]

I've never said I'm 99.9% sure about SMT4 so I cannot accept your bet. I admit the probability for SMT4 is very low around 0.1%. So do you accept bet of my 10$ vs. yours 10,000$?

You guys are so sure about no SMT4 so do not hesitate and take the easiest 10$ in your life
So you, Saylick... and somebody else would like to join?

Here's the issue. You say that the odds of SMT4 in Zen 3 are 0.1% (or about 1:1000) yet you blabber on about SMT4 being a part of Zen 3 every time the keyword "Zen 3" shows up in a thread. So what is it then? Those two statements are not complimentary. You can't talk like something is likely to happen yet admit that the numerical odds of it happening are less than 1%.

Here's my counter offer. Either A) You stick with your self admitted odds of 0.1% chance SMT4 are a part of Zen 3 (i.e. not likely), thus agreeing with us and never bring up again how Zen 3 will have SMT4, OR B) You stick with your belief that Zen 3 has SMT4 (because you're so sure that it has it) but then we get to see you eat a can of cat food if Zen 3 ships with only SMT2. We'll let you have the gourmet stuff (Fancy Feast) too.

 

[Glo.]

I've never said I'm 99.9% sure about SMT4 so I cannot accept your bet. I admit the probability for SMT4 is very low around 0.1%. So do you accept bet of my 10$ vs. yours 10,000$?

You guys are so sure about no SMT4 so do not hesitate and take the easiest 10$ in your life
So you, Saylick... and somebody else would like to join?


Why they would have different Zen3 for desktop? You can disable SMT in BIOS or possiby reduce it to SMT2.

10$ is not enough. You were so sure about SMT4 Zen 3, that only you betting 10000$, against mine 10$ on that would be appropriate bet.

Come on man. I need money for new PC.

 

[NostaSeronx]

Imho, it is better to go for single threaded. If needing similar route as SMT, it is better to copy Tremont's dual instruction stream tech. If it can be done via pure OoO it will then always be better than OoO+SMT.

If Genesis A0 is single-threaded, then Genesis B0 is probably single-threaded as well.

 

[Richie Rich]

It would not only be SMT4 in a server specific chiplet, bigger L2/L3 caches, chiplet aggregate capability, addon coprocessors/accelerators, ...
The desktop version all that would be cut.

Does Zen2 CPU chiplet exist in two different versions, one for server and another for desktop?

That is NOT what you have been saying all along.

I see that you and a lot of others lost confidence about SMT4 suddenly
Keyboard heroes talks strong but when it's about to bet money on that talk there is silence
Similar to stock market - how many AMD fanatics are having all savings in AMD stocks? It's too risky, they'd buy Intel stocks when it goes about big money

10$ is not enough. You were so sure about SMT4 Zen 3, that only you betting 10000$, against mine 10$ on that would be appropriate bet.

Come on man. I need money for new PC.

Do you know that by this ratio you are saying that you are 99.9% sure that Zen3 will have SMT4? Nice U-turn, man. I appreciate you changed opinion

If I remember correctly I suggested half year ago 60% or 80% probability for SMT4 and this would mean ratio 1:3 or 1:4. Today I would suggest lower than 50%, maybe 25-30%, this means ratio 3:1. So I can't accept 1:1000 ratio that would be bad deal for me, 3000 times worse than my expectation. However I will accept anything above 4:1 (80% SMT2 vs. 20% SMT4), 9:1 (90% probability SMT2, 10% SMT4) or 99:1 (99% probability). Higher is better deal for me.


Guys, just do not be cowards and write down your percentage of SMT4 probability for Zen3. Lets see how big your real confidence is. This will separate men from keyboard heroes certainly.


Stop with the confrontational, inflammatory posting.


esquared
Anandtech Forum Director

 

[krumme]

0.Rich%

 

[DrMrLordX]

I see that you and a lot of others lost confidence about SMT4 suddenly

Pot calling the kettle black.

Keyboard heroes talks strong

. . . again? How many times can you do this in one post?

Guys, just do not be cowards and write down your percentage of SMT4 probability for Zen3.

0%, since AMD already told us there would be SMT2 in Milan.

Lets see how big your real confidence is. This will separate men from keyboard heroes certainly.

Pssh, like I'd trust you to tell me that.

 

[amrnuke]

I see that you and a lot of others lost confidence about SMT4 suddenly

1. I never said SMT4 would be in Zen3. You did.
2. I have never said anything (good or bad) about SMT4 specifically.
3. YOU are the one who lost confidence about SMT4 suddenly.

If I remember correctly I suggested half year ago 60% or 80% probability for SMT4 and this would mean ratio 1:3 or 1:4. Today I would suggest lower than 50%, maybe 25-30%, this means ratio 3:1.

But 6 hours ago before that post, on the same day, you said the probability was "very low around 0.1%".

I've never said I'm 99.9% sure about SMT4 so I cannot accept your bet. I admit the probability for SMT4 is very low around 0.1%.

It's hard to argue with someone who seems to have no idea what they're even thinking. Part of me hopes you're doing this intentionally, because if not, I would seriously worry about your health.

FWIW, there will NOT be SMT4 on Zen3.

 

[thigobr]

I was expecting a bigger performance jump between LPDDR4 4266MHz and DDR4 3200MHz (4800U vs 4800H)

 

[lobz]

I was expecting a bigger performance jump between LPDDR4 4266MHz and DDR4 3200MHz (4800U vs 4800H)

15/25W vs 45W counts a lot more.

 

[RetroZombie]

Does Zen2 CPU chiplet exist in two different versions, one for server and another for desktop?

No. And why zen3 shouldn't exist in two different versions?

You have Forrest Norrod painting zen3 has super duper and you have the amd slides saying it's just 15% ipc increase. Maybe they are talking of different product, one for desktop and another for the datacenter.

It's funny that it's you who push smt4 up and up. And if some mentions the possibility of existing like i did it's down and down...

 

[Thibsie]

15% at least IPC.
Add process improvement (TDP/frequency scaling).

Should be more than 15% performance.

 

[NTMBK]

No. And why zen3 shouldn't exist in two different versions?

You have Forrest Norrod painting zen3 has super duper and you have the amd slides saying it's just 15% ipc increase. Maybe they are talking of different product, one for desktop and another for the datacenter.

1. 15% IPC improvement is nothing to sneeze at! For a year on year improvement to the best performance in the world, it's pretty damn good. Especially after 5 years of 0% improvements from Intel.

2. IPC depends on the workload you measure. Depending on what was improved, different workloads will see different gains. Maybe FPU bound code doesn't gain much, but stall-heavy integer code sees big gains? We'll just have to wait and see!

 

[Veradun]

No. And why zen3 shouldn't exist in two different versions?

You have Forrest Norrod painting zen3 has super duper and you have the amd slides saying it's just 15% ipc increase. Maybe they are talking of different product, one for desktop and another for the datacenter.

It's funny that it's you who push smt4 up and up. And if some mentions the possibility of existing like i did it's down and down...

Or maybe "performance" has a broader meaning than just compute.

 

[amrnuke]

Or maybe "performance" has a broader meaning than just compute.

Exactly. But also, porque no los dos?

It's possible that with the redesign they could have optimized even further for single/lightly threaded performance (gaming, Office), and also multi threaded performance, but doing so via slightly different means. And some of the changes will benefit both. I also really like that AMD are utilizing the process node changes so much, to help build a lead. Marching ahead with TSMC with 7% performance or 10% power benefits (assuming N7P).

Really will be interesting to deep-dive the changes.

 

[DisEnchantment]

The following merged Linux kernel patches suggest major changes in the Load/Store architecture of Zen3/Family 19h

SMCA Patches for Family 19h
New Load store architecture for Zen3/Family 19h [Jan 10th, 2020]

https://github.com/torvalds/linux/commit/89a76171bf50bd20d44338408b8c09433c302956#diff-468c185c1fd58d8f491a5eed2a15825b

"An ECC error was detected on a data cache read by a probe or victimization",
"An ECC error or poison bit mismatch was detected on a tag read by a probe or victimization",
"A parity error was detected in an SCB entry state field by any access",
"A parity error was detected in an SCB entry address field by any access",
"A parity error was detected in an SCB entry data field by any access",

Changes in L3 hierarchy suggested by this perf patch

https://github.com/torvalds/linux/commit/e48667b865480d8bf0f1171a8b474ffc785b9ace#diff-da441899381d8c9f80c02f02999a5c90

When I read the MCA error strings for the LS_V2 it strikes me that there is some kind of correlation with the patents applications made public recently.
Patent Applications
20200065275, 20200099993, 20190108861, 20190199617
See also this post

Page 11 - Discussion - Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

Page 11 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

It seems to me that the Zen3 could in fact be the next stepping stone for the chiplet and Infinity Architecture instead of the direct jump and everything implemented in Zen4.
Zen1 introduced NUMA MCM processors.
Zen2 introduced cache coherent Chiplet processors
Zen3 will introduce something as radical as Zen1/2

[WILD SPECULATION]

Reading the error strings it seems, the L3 could be poisoned by a Load/Store/eviction(victimization) AND a "probe"
The probe mechanism is described in the above patents and is triggered by the coherency probe messages from other CCXs. There are mentions of address and state as described in the patents.
CCXs are cache coherent at L3 level.
This implies that some extent of the new on-chip communication coherent fabric is implemented in Zen3. Fingers crossed.

What could this mean
- A direct CCX to CCX communication is possible without the IOD.
- The IOD serves as the base die where the routing logic resides.
- Active blocks could still reside on the IOD but the comminication is not hierachical but rather bus/mesh oriented.
- There could be a reduction in latency compared to Zen for inter CCX due to direct die to die communication
- Reduction in memory access latency as the CCXs can access the memory controller attached to a coherent slave

The Zen IMC is also cache aware and can do speculative access. This is described in some patents in the past. I am not sure it will apply to Zen3 but it does makes sense.
This kind of implementation has already been done before albeit not with a leading edge process and high performance cores... and guess what, made public only recently.
Links for the first ever implementation of a NoC with chiplet and active interposer.

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

fuse.wikichip.org

Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures

We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D...

ieeexplore.ieee.org

[/WILD SPECULATION]

 

[Saylick]

You know, now that I think about it... I was reminded of this Anandtech article: https://www.anandtech.com/show/1559...hitecture-connecting-everything-to-everything

While the article shows cache coherency between 8 GPUs, I don't see why it couldn't be the same with 8 CCDs...

Literally just replace the GPUs with CCDs and the EYPC processor with the IOD in this diagram: