DisEnchantment
Golden Member
- Mar 3, 2017
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You are right actually. I was imagining the Zen layout. the Zen2 CCD has one IFOP.There shouldn’t be any serdes between the 2 on die CCX and the fabric link on the die. That seems to be what you are implying here? That would be a waste.
I think there will be a new IO die or at the very least it will be updated. EPYC is using a lot of power for the interconnects/IF, which could be responsible for it not being able to sustain high clocks with 8 chiplets within that thermal envelope.We probably don’t get a new IO die until Zen 4 with DDR5 and pci-express 5
Yeah, the moment we want to piece together some of the pieces from info in public domain, the more we know so much info is missing.So, how are they going to get the extra bandwidth? Doubling the paths to 64-bytes kind of seems unlikely. Perhaps the L1 will be able to load more than 2 x 32-bytes per clock? That may improve performance significantly without even increasing the number of AVX units. I was thinking that they would go up to 3 AVX256 units, but it may be all cache improvements. It would be great if they managed to reduce latency in L1/L2 to make up for the slightly higher L3 latency.
Tbh, I am really looking forward to such a change. The interconnect and core topology seems rather more interesting to me.Since AMD's WSA with GloFo runs out early next year I expect them to stop using GloFo for the Zen 3 IOD. Since the IOD will then change node anyway there likely will be Zen 3 specific changes to it as well. I wouldn't rule out more significant changes to the package layout either.