NostaSeronx
Diamond Member
- Sep 18, 2011
- 3,705
- 1,231
- 136
There is also them hiring with 5nm in mind in Q1:
Austin => Join a global package reliability team that drives component and board-level reliability activities across AMD's 5nm/7nm IC and graphics-card products that employ advanced flipchip and chiplet package constructions.
Singapore => The Singapore-based Packaging Reliability Engineer would lead board-level reliability activities for 5nm/7nm AMD CPU/GPU/APU and graphic-card products
Hydrabad, India => Sep 2018 – Present. Front-end integration team: Synthesis over 7nm/5nm
Silicon Designer 2 => Physical Design CAD Engineer at AMD on the latest 5 nm & 7 nm FinFET based technologies
Senior Design Engineer => high performance Microprocessors,SERDES, DDRs, DAC's, ADC's, PLL's in tsmc7 and 5nm technologies.
=> May 2019 – Aug 2019. -Supported L3 Cache Physical Design team -Worked with the TSMC 7nm and 5nm
Layout Engineer => tsmc 5nm, 7nm
Silicon Designer 2 => TSMC (7nm, 6nm, 5nm)
Mask design technician => Jun 2019 – Present. Mixed-Signal layout design in 5nm/7nm FinFET technology
Physical Design Engineer => Five Successful Tapeout @7nm Technology. Starting @5nm Technology.
=> 2013-2018 => L2 Macro -5nm FinFET Test Chip Layout & SRAM Memory Compiler layout design in TSMC 5nm FinFET
Silicon designer 2 => Developing scripts in Python towards port migration of 7nm to 5nm using Python gdspy package.
Senior R&D Process Integration Engineer. TSMC. July 2017 – March 2018 which did N5 FEOL logic process integration became a Senior Product Development Engineer at AMD.
A&MS Layout Designer Engineer => N5 TSMC FINFET, HDSP, UHD2PRF and HDRF2P Testchip and compiler development from scratch for Hi-Silicon and AMD @Synopsys
Also, hired R&D Engineer II => Project/ comments: N5 for Hi Silicon and AMD
Zen3 at worst is 6nm EUV. With no improvement over Zen2.
Zen3 at best is 5nm EUV. With "tremendous" improvement over Zen2.
AMD showcased Vega 7nm before Apple A12 and showcased Rome 7nm w/ Vega 7nm after A12. It doesn't make sense for AMD to be behind in process node. Especially with a more simple and smaller die on a proven SP3/AM4 platform. Swap out 7nm, for easy 5nm gains with HMC SiGe PFET.
Navi2x is stuck on 7nm family;
7nm 3rd-generation DUV: PS5, XSX, XSS
7LPP RDNA2 IP for Samsung <-
5LPE RDNA2 IP for Samsung <- Both of these are identical so it is really Low-power 7LPP or High-performance 5LPE.
Zen3 so far on the APU side;
Rembrandt 40h-4Fh is 5nm, thus 50h-5Fh Cezanne is 5nm. Simply, because the model number is later. So, Zen3 IP is on 5nm.
We already have profiles "Experience in X86 PC Architecture Rembrandt APU of AMD processors" and an earlier pre-cleansed profile said Rembrandt is 5nm.
Van Gogh/Mero basically being the DDR4 version of 197.1 mm2 Lockhart-GDDR6 edition. Has Navi2x being 7nm as well.
Rembrandt having (LP)DDR4 [FP7] and (LP)DDR5 [FP7r2] being a true mainline processor is after the above. This means Navi3x is 5nm.
Austin => Join a global package reliability team that drives component and board-level reliability activities across AMD's 5nm/7nm IC and graphics-card products that employ advanced flipchip and chiplet package constructions.
Singapore => The Singapore-based Packaging Reliability Engineer would lead board-level reliability activities for 5nm/7nm AMD CPU/GPU/APU and graphic-card products
Hydrabad, India => Sep 2018 – Present. Front-end integration team: Synthesis over 7nm/5nm
Silicon Designer 2 => Physical Design CAD Engineer at AMD on the latest 5 nm & 7 nm FinFET based technologies
Senior Design Engineer => high performance Microprocessors,SERDES, DDRs, DAC's, ADC's, PLL's in tsmc7 and 5nm technologies.
=> May 2019 – Aug 2019. -Supported L3 Cache Physical Design team -Worked with the TSMC 7nm and 5nm
Layout Engineer => tsmc 5nm, 7nm
Silicon Designer 2 => TSMC (7nm, 6nm, 5nm)
Mask design technician => Jun 2019 – Present. Mixed-Signal layout design in 5nm/7nm FinFET technology
Physical Design Engineer => Five Successful Tapeout @7nm Technology. Starting @5nm Technology.
=> 2013-2018 => L2 Macro -5nm FinFET Test Chip Layout & SRAM Memory Compiler layout design in TSMC 5nm FinFET
Silicon designer 2 => Developing scripts in Python towards port migration of 7nm to 5nm using Python gdspy package.
Senior R&D Process Integration Engineer. TSMC. July 2017 – March 2018 which did N5 FEOL logic process integration became a Senior Product Development Engineer at AMD.
A&MS Layout Designer Engineer => N5 TSMC FINFET, HDSP, UHD2PRF and HDRF2P Testchip and compiler development from scratch for Hi-Silicon and AMD @Synopsys
Also, hired R&D Engineer II => Project/ comments: N5 for Hi Silicon and AMD
Zen3 at worst is 6nm EUV. With no improvement over Zen2.
Zen3 at best is 5nm EUV. With "tremendous" improvement over Zen2.
AMD showcased Vega 7nm before Apple A12 and showcased Rome 7nm w/ Vega 7nm after A12. It doesn't make sense for AMD to be behind in process node. Especially with a more simple and smaller die on a proven SP3/AM4 platform. Swap out 7nm, for easy 5nm gains with HMC SiGe PFET.
Navi2x is stuck on 7nm family;
7nm 3rd-generation DUV: PS5, XSX, XSS
7LPP RDNA2 IP for Samsung <-
5LPE RDNA2 IP for Samsung <- Both of these are identical so it is really Low-power 7LPP or High-performance 5LPE.
Zen3 so far on the APU side;
Rembrandt 40h-4Fh is 5nm, thus 50h-5Fh Cezanne is 5nm. Simply, because the model number is later. So, Zen3 IP is on 5nm.
We already have profiles "Experience in X86 PC Architecture Rembrandt APU of AMD processors" and an earlier pre-cleansed profile said Rembrandt is 5nm.
Van Gogh/Mero basically being the DDR4 version of 197.1 mm2 Lockhart-GDDR6 edition. Has Navi2x being 7nm as well.
Rembrandt having (LP)DDR4 [FP7] and (LP)DDR5 [FP7r2] being a true mainline processor is after the above. This means Navi3x is 5nm.
Last edited: