Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[DrMrLordX]

Your prediction is odd as always.

10ESF is their last in-house node with significant wafer volume and (apparently) decent yields. Everything beyond that is going to be . . . problematic. Genoa is going to make it extremely difficult on them. It will hit them where it hurts moreso than Milan which is already causing Intel severe headaches.

Intel has a chance to right the ship with 20A. It's their next in-house process which may enjoy significant upticks in wafer volume versus Intel 4/7nm and Intel 3. That's all assuming Gelsinger managed to finally put in some orders for more EUV equipment!

 

[NostaSeronx]

That's all assuming Gelsinger managed to finally put in some orders for more EUV equipment!

Why bother with EUV...


JFIL for "real 5nm" logic is expected to be ready in 2025.

Intel used JFIL for 450mm first print => "------ visited Austin on Thursday, and here you see him reflected in a huge 450mm wafer, produced by Intel using the Molecular Imprints nanolithography tool. This is the first system capable of patterning such large wafers, and it pushes the resolution below 24 nanometers."

With that conference occurring in March 2022 previewing hitting early "real 3nm" logic targets.

0.4x the cost to operate.
0.1x the power to operate.
Significantly cheaper than EUV at a given wph.
~2018 = NAND Target
~2020 = DRAM Target (GloFo's eNVM)
~2023 = Logic Target (GloFo's 7LPc and lower; Leading Performance-Cost nodes)
HVM NZxC = 2025, with a lot more tools being shipped than EUV

I have to find the GlobalFoundries JFIL stuff I kept tucked away. With a proposed plan of having Dresden, Malta, and Singapore doing 7nm and lower at low-cost.

 

[JasonLD]

10ESF is their last in-house node with significant wafer volume and (apparently) decent yields. Everything beyond that is going to be . . . problematic. Genoa is going to make it extremely difficult on them. It will hit them where it hurts moreso than Milan which is already causing Intel severe headaches.

Intel has a chance to right the ship with 20A. It's their next in-house process which may enjoy significant upticks in wafer volume versus Intel 4/7nm and Intel 3. That's all assuming Gelsinger managed to finally put in some orders for more EUV equipment!

According to Mizuho report you seem to religiously basing your predictions on, Intel's 7nm(Intel 3/4) capacity is going to be about 1/3 of 10nm capacity in 2022~2023, which should be enough volume for Meteor Lake based SoCs. Intel only needs compute tiles to be based on their 7nm unlike their current lineups which entire processor has to be fabricated on same process.
I don't see why Intel should have a volume problem (other than obvious global chip shortages) due to their own 3/4 processes when significant portion of their future SoCs will still be based on their 10ESF and TSMC's processes.

 

[NTMBK]

If CES 2022 even happens... a LOT of companies have backed out.

AMD have cancelled their in person appearance at CES, but are still going to do a livestream:

AMD and MSI Cancel Physical Presence at CES 2022

MSI joins companies that canceled their CES physical presence.

www.tomshardware.com

 

[DrMrLordX]

According to Mizuho report you seem to religiously basing your predictions on

Even if the numbers are off by some non-trivial percent, the implications of those numbers in relation to Intel's 14nm and 10nm capacity remains. Intel is taking a big hit in capacity.

Intel's 7nm(Intel 3/4) capacity is going to be about 1/3 of 10nm capacity in 2022~2023, which should be enough volume for Meteor Lake based SoCs

Intel has to share that node with Granite Rapids. They're already moved all their dGPU projects off Intel nodes. Consider the implications.

AMD have cancelled their in person appearance at CES, but are still going to do a livestream:

AMD and MSI Cancel Physical Presence at CES 2022

MSI joins companies that canceled their CES physical presence.

www.tomshardware.com

Not surprising. Tech conferences just aren't going to be the same for awhile, if ever.

 

[soresu]

Not surprising. Tech conferences just aren't going to be the same for awhile, if ever.

Yeah to be honest the old tech conference PR presentations model is outdated.

With real time game engines, LED walls and green screens they can easily create product presentations that bring the company PR people into the action rather than dumbly standing in front of some big screens with pre rendered slides.

News media is already starting to use these technologies so it seems very odd for the tech companies to still be using the old ways.

 

[DisEnchantment]

I compiled some of the microprocessor IP blocks used in various AMD SoCs, I wonder if someone on here knows more than what I could find in this list.

MP0 CCP/PSP [ARM] --> Introduced in Zen1, 1x per SoC
MP1 SMU [Cadence LX3/6] --> Introduced in Zen1, 1x per CCD with one master SMU
MP2 SFH [ARM] --> Introduced in Renoir, 1x per SoC
MP5 Microprocessor5 Management Controller [Cadence LX3/6] --> Introduced in Zen2, 1x per CCD
MPDMA [Cadence ?] --> To be introduced in Zen4, 1x per SoC
MPIO [ARM ?] --> To be introduced in Zen4, 1x per SoC
AIM-T [Cadence LX6] --> To be introduced in RMB, 1x per SoC
C5/Q6 [Cadence] --> Introduced in VGH, 1x per SoC
ISP [Cadence] --> Introduced in CZN, 1x per SoC
ACP Cadence HiFi based --> Introduced in Fusion APUs, probably HiFi 5 with RMB, 1x per SoC
A55 [ARM]--> Introduced in VGH, I think this one performs some AOP functions, 1x per SoC

I did not include IP blocks used by the GPUs, those also used a lot of microprocessor IPs.

@NostaSeronx Do you care to fill in additional info I don't have (with some sources, links if possible)

Update:
Removed Color

 

[mikk]

10ESF is their last in-house node with significant wafer volume and (apparently) decent yields. Everything beyond that is going to be . . . problematic. Genoa is going to make it extremely difficult on them. It will hit them where it hurts moreso than Milan which is already causing Intel severe headaches.

Process node capacity and micro-architecture performance are two different things, don't mix it up. AMD has a low capacity in comparison to Intels but this does not automatically mean Zen 4 and Zen 5 are poor performer. And it also does not mean Meteor, Arrow, Lunar are slowing down. And regarding process capacity Intel might mix it up with TSMC and in-house capacity because Intel is beside Apple the main customer of 4nm and 3nm, but this is speculative at this point. Same for the capacity of Intels 3/4 node in 2023 and during 2024.

 

[DrMrLordX]

Process node capacity and micro-architecture performance are two different things, don't mix it up.

I'm not mixing up anything. Wait and see.

 

[NostaSeronx]

MPDMA [Cadence ?] --> To be introduced in Zen4, 1x per SoC
MPIO [ARM ?] --> To be introduced in Zen4, 1x per SoC

@NostaSeronx Do you care to fill in additional info I don't have (with some sources, links if possible)

MPDMA is refereed with DVM
MPIO is referred with UBM;
"xGMI, WAFL, PCIe, and other training"
"UBM system platform topology discovery on system power up and dynamic communication between various system software components running on AMD processor and PCIe Hot Plug, NVMe and SATA Devices attached to the DFCs"
- https://chipsandcheese.com/2021/08/23/details-on-the-gigabyte-leak/

UBM is mentioned with: "Technical owner for firmware for supporting next generation interconnect technologies both for AMD proprietary and industry standards like PCIe, CXL, MCTP, UBM, and USB4."
- Firmware Engineer- 118701
MPDMA is mentioned with: "Design and develop diagnostics software for validation of DVM and MPDMA Hardware IP and Firmware features on pre-silicon platforms (FPGA, Simulation, SOC Emulation, etc.) and post-silicon system (silicon and platform)"
- Diagnostics Software Engineer - Distributed Virtual Memory (DVM)-110683

Appears to all be ARM-related IP for servers.

MPIO;
xGMI = AMD
WAFL = NVRAM, Cadence or Synopsys or AMD's Prop UMC
PCIe = Cadence or Synopsys or AMD's Prop Data Fabric1
UBM = Cadence or Synopsys or AMD's Prop Data Fabric2

MPDMA;
DVM = ARM's Coherent Hub Interface (AXI5, ACE5 and AHB5 protocols)

ARM IP <-> AMD+EDA PHY/Control Units

 

[Hans de Vries]

Intel used JFIL for 450mm first print => "------ visited Austin on Thursday, and here you see him reflected in a huge 450mm wafer, produced by Intel using the Molecular Imprints nanolithography tool. This is the first system capable of patterning such large wafers, and it pushes the resolution below 24 nanometers."

Their website hasn't been updated since 2014 or so unfortunately....

About CNT – Canon Nanotechnologies

cnt.canon.com

Your quote is from may 9, 2013....

https://flic.kr/p/ejjkBu

 

[eek2121]

I'm not mixing up anything. Wait and see.

Intel is not going to have issues. They have a partnership with TSMC. Intel 4 doesn’t need to produce as many chips as Intel 7 because they will be able to mix and match going forward. The process itself is also in a very good place.

I expect AMD will have it’s hands full for quite a while.

 

[Doug S]

Their website hasn't been updated since 2014 or so unfortunately....

About CNT – Canon Nanotechnologies

cnt.canon.com

Your quote is from may 9, 2013....

https://flic.kr/p/ejjkBu

Just the reference to 450mm dates it every bit as well as seeing a reflected image of two presidents ago; the industry gave up on 450mm years ago.

It is laughable that anyone would believe Intel is going to resurrect a technology that no one has heard anything about for nearly a decade but have kept quiet on that. And why would they be taking delivery of ASML's first high NA EUV scanner if they were going to use JFIL?

The guy you're replying to believes in google "research" way too much!

 

[JasonLD]

Even if the numbers are off by some non-trivial percent, the implications of those numbers in relation to Intel's 14nm and 10nm capacity remains. Intel is taking a big hit in capacity.



Intel has to share that node with Granite Rapids. They're already moved all their dGPU projects off Intel nodes. Consider the implications.

Not sure why you keep ignoring the fact that future Intel products are no longer monolithic and will be mixed with their older processes and TSMCs, which will significantly reduce the volume requirement.

 

[NostaSeronx]

Their website hasn't been updated since 2014 or so unfortunately....

Technical Library – Canon Nanotechnologies

cnt.canon.com

It has research papers up to 2020: SPIE AL 2020: Lithography-today-Challenges-and-solutions-across-a-diverse-market

Current performance of Canon’s NZ2C multi-station cluster tool is summarized below:
- An overlay of 3.2nm has been achieved.
- Throughput is now at 100 wafers per hour
- Defectivity of 0.2/cm2 has been demonstrated

From 2019:


March 2022 SPIE conference is previewing 3nm Logic capability.

Defect density: 0.01 is wanted for HVM Logic.

2021 = 0.05 (Feb 2021 = 0.07 defect density @ Kioxia)
2022 = 0.02 <-- Insert of tools into fab
2023 = 0.01
2024 = 0.008, etc however they want to reduce defect density for logic.

Just the reference to 450mm dates it every bit as well as seeing a reflected image of two presidents ago; the industry gave up on 450mm years ago.

It is laughable that anyone would believe Intel is going to resurrect a technology that no one has heard anything about for nearly a decade but have kept quiet on that. And why would they be taking delivery of ASML's first high NA EUV scanner if they were going to use JFIL?

It was only meant to note that they were using a JFIL tool. Mind you that a bunch of Sematech/Albany at GlobalFoundries who were JFIL aficionados are now TD lithography insert leads at Intel.

Phase IV at Canon = "Additionally, Canon Nanotechnologies, formerly Molecular Imprints, became a subsidiary in 2014, and we are accelerating the development of next-generation semiconductor manufacturing equipment that uses nanoimprint lithography, which will make it possible to achieve both miniaturization and cost reductions for semiconductor devices."

Phase V at Canon = "The group will also utilize nanoimprint lithography technology to enter the leading-edge segment of semiconductor production. Currently, most of the technical challenges related to nanoimprint lithography have been solved. Going forward, the group will work with a semiconductor device manufacturer to start mass production and will commence testing with the goal of expanding the usage of this technology."

1. GlobalFoundries (No EUV; Cost-prohibitive ramp if EUV; JFIL insert likely)
2. Intel (Partial EUV ramp; Not as big as Samsung or TSMC; JFIL depends on hitting goals before EUV/Hi-Na EUV)
3. China Foundries (No patent barricade; Anyone can technically do NIL)

NZ2C isn't the Logic HVM tool, it is however that one => NZ3C is also being developed as a next-generation machine, at 200wph, the overlay is <3.5nm, 0.01DD. (2016/2017, but no reveal yet)

Which is the leap-frog over EUV tool and insert against 193i. Where it costs 0.4x to operate and 0.1x to power compared to 193i.

 

[Exist50]

Just the reference to 450mm dates it every bit as well as seeing a reflected image of two presidents ago; the industry gave up on 450mm years ago.

It is laughable that anyone would believe Intel is going to resurrect a technology that no one has heard anything about for nearly a decade but have kept quiet on that. And why would they be taking delivery of ASML's first high NA EUV scanner if they were going to use JFIL?

The guy you're replying to believes in google "research" way too much!

It's Nosta. Very safe to ignore.

 

[PJVol]

I wonder if someone on here knows more than what I could find in this list.

Not that I know for sure, but taking wild guess here, that MP5 are the SMU slaves, so that the master functionality has moved to a separate controller (mp1) since Zen2.

 

[DrMrLordX]

They have a partnership with TSMC.

And you don't see that as a problem? TSMC is trying to gut their manufacturing capabilities.

Intel 4 doesn’t need to produce as many chips as Intel 7 because they will be able to mix and match going forward.

They still need compute and GPU tiles to be on bleeding-edge processes. It's not like the tiled approach just makes all their problems go away.

The process itself is also in a very good place.

Based on what? Loihi 2? Intel had to take the Ponte Vecchio tiles off 7nm/Intel 4 for a reason.

I expect AMD will have it’s hands full for quite a while.

AMD will continue selling everything they make. The only problem will be that AMD may not be taking enough N5 wafers.

Not sure why you keep ignoring the fact that future Intel products are no longer monolithic

I'm not. At all. How much die area do you think Intel will save moving from Sapphire Rapids to Granite Rapids thanks to tiling with old processes? Remember that Granite Rapids is meant to be competition for Genoa and Bergamo. How much of that product do you think can be 10ESF without taking a performance hit? Allegedly Intel is getting maybe 20wkpm of TSMC N3, and that is (presumably) going to their dGPUs, GPU tiles, and possibly Arrow Lake compute tiles. How much of that will be left for Granite Rapids?

Seeing the problem yet?

 

[Bigos]

I compiled some of the microprocessor IP blocks used in various AMD SoCs, I wonder if someone on here knows more than what I could find in this list.

MP0 CCP/PSP [ARM] --> Introduced in Zen1, 1x per SoC
MP1 SMU [Cadence LX3/6] --> Introduced in Zen1, 1x per CCD with one master SMU
MP2 SFH [ARM] --> Introduced in Renoir, 1x per SoC
MP5 Microprocessor5 Management Controller [Cadence LX3/6] --> Introduced in Zen2, 1x per CCD
MPDMA [Cadence ?] --> To be introduced in Zen4, 1x per SoC
MPIO [ARM ?] --> To be introduced in Zen4, 1x per SoC
AIM-T [Cadence LX6] --> To be introduced in RMB, 1x per SoC
C5/Q6 [Cadence] --> Introduced in VGH, 1x per SoC
ISP [Cadence] --> Introduced in CZN, 1x per SoC
ACP Cadence HiFi based --> Introduced in Fusion APUs, probably HiFi 5 with RMB, 1x per SoC
A55 [ARM]--> Introduced in VGH, I think this one performs some AOP functions, 1x per SoC

I did not include IP blocks used by the GPUs, those also used a lot of microprocessor IPs.

@NostaSeronx Do you care to fill in additional info I don't have (with some sources, links if possible)

I would like to ask you to stop using colors. The dark background makes the dark-purple font unreadable.

 

[turtile]

I'm not. At all. How much die area do you think Intel will save moving from Sapphire Rapids to Granite Rapids thanks to tiling with old processes? Remember that Granite Rapids is meant to be competition for Genoa and Bergamo. How much of that product do you think can be 10ESF without taking a performance hit? Allegedly Intel is getting maybe 20wkpm of TSMC N3, and that is (presumably) going to their dGPUs, GPU tiles, and possibly Arrow Lake compute tiles. How much of that will be left for Granite Rapids?

Seeing the problem yet?

I agree. There's no way Intel is going to outperform AMD in the data center until 2025 or later. Intel may beat AMD in performance between generations but I don't see them winning in energy efficiency. Genoa will likely land in the big data center players in July of this year and Sapphire Rapids, which is a process behind, is still missing. And since Genoa is out first, many customers will have the AMD platform and they will find it easier to simply drop in next-gen AMD instead of switching to Intel.

TSMC isn't gaining any market share with Intel's GPU business because it only eats into Nvidia and AMD orders. Intel will probably use the rest of 3nm for mobile to 'compete with Apple'. AMD is rumored to use Samsung 3nm for low-cost mobile.

Intel is a manufacturing business first and design business second. They simply can not let their fabs idle if they want to hold on to profits while expanding their fabs at a breakneck pace. Intel does not have enough EUV machines to move much of the production to Intel 4 and that's going to hurt.

 

[Doug S]

And you don't see that as a problem? TSMC is trying to gut their manufacturing capabilities.

How?

They can't stop Intel from developing their own processes. TSMC offering a better process does not gut Intel's fabs. Intel choosing to use them might, but that's on them not TSMC.

If you own a lawn care business but hire some other service to mow your own lawn instead because they do a better job than your employees do, is that other service responsible for "gutting" your business if the word gets out about it?

 

[jpiniero]

They can't stop Intel from developing their own processes. TSMC offering a better process does not gut Intel's fabs. Intel choosing to use them might, but that's on them not TSMC.

Intel can't afford to continue with the fabs if they spend what it would take to fab key stuff at TSMC. Unless they get the US Government to pay for it.

 

[Doug S]

Intel can't afford to continue with the fabs if they spend what it would take to fab key stuff at TSMC. Unless they get the US Government to pay for it.

It is their choice alone to "fab key stuff" at TSMC. It isn't TSMC "gutting" them.

 

[DrMrLordX]

It is their choice alone to "fab key stuff" at TSMC. It isn't TSMC "gutting" them.

They either take wafers from TSMC or they lose volume and its associated revenue. It looks like Gelsinger has already made his choice. Intel is still losing volume anyway, but not by as much by choosing to take TSMC wafers. TSMC isn't going to make this cheap. Further process missteps are not going to be pretty. And on top of all this, remember, AMD now has a decisive advantage in the server room. Genoa is already one generation ahead, and I see no indicator that Intel will catch up.

It was already embarassing for Intel when IceLake-SP came out stupidly late and it couldn't even beat Rome decisively (or at all, in many cases). What happens when Granite Rapids hits and it can't beat Genoa or Bergamo?

Once the first public Genoa benchmarks hit sites like servethehome, we should be able to make some guesstimates about what Intel will have to do to beat it, and whether or not that will even be possible within one generation. My prediction is that Genoa's performance this year should be quite impressive. Better than the Rome->Milan transition.

 

[Joe NYC]

I would like to ask you to stop using colors. The dark background makes the dark-purple font unreadable.

I would like you to change your forum handle to Karen, so that your posts can be viewed in proper color.





Personal insults are not allowed.


esquared
Anandtech Forum Director