Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[eek2121]

Supplies may be better now, but we were having difficulty getting Milan chips. There were rumors of a covid outbreak late 2021 at packaging facilities in Malaysia that may have caused a massive backlog.

A lot of people are still dismissive of AMD as a serious enterprise solution, but part of this is that the server market just moves slower. A lot of times it is longer term deals or a large number of servers spec’ed and then purchased over several years. I don’t really think Intel will have that strong of competition for a while yet so AMD still has some time to gain mindshare and market share. Intel has some MCM / stacked solutions in the pipeline, but AMD also has a lot of things coming with Milan-X3D, Genoa, possibly Genoa-X3D, and Bergamo.

Can confirm, Milan was near impossible to get for quite a while.

 

[BorisTheBlade82]

FYI
At the 3DCenter Forum some guys are speculating that the IOD for Genoa (and maybe Bergamo as well) might still be some kind of 12nm from GF. This is reinforced by the info that GF licensed DDR5, PCIE5 and USB4 IP for 12LP+, see https://news.synopsys.com/2020-09-2...o-of-DesignWare-IP-for-12LP-FinFET-Solution,1

What do you think? What was the source for the speculation that the IOD could be 7nm/6nm TSMC? Could they probably split processes for server and client?

 

[Kepler_L2]

FYI
At the 3DCenter Forum some guys are speculating that the IOD for Genoa (and maybe Bergamo as well) might still be some kind of 12nm from GF. This is reinforced by the info that GF licensed DDR5, PCIE5 and USB4 IP for 12LP+, see https://news.synopsys.com/2020-09-2...o-of-DesignWare-IP-for-12LP-FinFET-Solution,1

What do you think? What was the source for the speculation that the IOD could be 7nm/6nm TSMC? Could they probably split processes for server and client?

We already know the IOD die size for Genoa is smaller than Rome/Milan, so it has to be 6nm.

 

[Saylick]

FYI
At the 3DCenter Forum some guys are speculating that the IOD for Genoa (and maybe Bergamo as well) might still be some kind of 12nm from GF. This is reinforced by the info that GF licensed DDR5, PCIE5 and USB4 IP for 12LP+, see https://news.synopsys.com/2020-09-2...o-of-DesignWare-IP-for-12LP-FinFET-Solution,1

What do you think? What was the source for the speculation that the IOD could be 7nm/6nm TSMC? Could they probably split processes for server and client?

AMD revised it's WSA with GF, so perhaps there's some product in the future uses that licensed IP but targets the embedded sector.

 

[Hitman928]

We already know the IOD die size for Genoa is smaller than Rome/Milan, so it has to be 6nm.

I don't believe the difference is very large and 12LP+ comes with a density increase over 14 nm so that doesn't exclude the possibility of 12LP+ being used. I believe the IOD size will largely be set by the pad/bump count anyway so going to denser processes won't have much effect on die size unless they allow for tighter pad/bump pitches that AMD can utilize. Going to 7/6 nm was largely seen as a way to reduce the power of the IOD but even then the benefit would not be as large as you might think due to the nature of the circuitry inside (MS/IO) that doesn't scale nearly as well as digital logic. I don't know what process AMD is using, but I wouldn't be shocked if it was 12LP+. They'd be giving up some degree of power savings but switching to 7/6 nm would also eat into their wafer allocation as well which would reduce the amount of supply of CPUs and GPUs they could provide. AMD's moving to 5 nm for the compute dies at the same time so that will help, but I also expect products using 7/6 nm to still be in rather high demand for at least a couple of years. We'll see what AMD has done soon enough.

 

[maddie]

I don't believe the difference is very large and 12LP+ comes with a density increase over 14 nm so that doesn't exclude the possibility of 12LP+ being used. I believe the IOD size will largely be set by the pad/bump count anyway so going to denser processes won't have much effect on die size unless they allow for tighter pad/bump pitches that AMD can utilize. Going to 7/6 nm was largely seen as a way to reduce the power of the IOD but even then the benefit would not be as large as you might think due to the nature of the circuitry inside (MS/IO) that doesn't scale nearly as well as digital logic. I don't know what process AMD is using, but I wouldn't be shocked if it was 12LP+. They'd be giving up some degree of power savings but switching to 7/6 nm would also eat into their wafer allocation as well which would reduce the amount of supply of CPUs and GPUs they could provide. AMD's moving to 5 nm for the compute dies at the same time so that will help, but I also expect products using 7/6 nm to still be in rather high demand for at least a couple of years. We'll see what AMD has done soon enough.

The power savings are also quite large, ~ 40% as stated by GloFlo.

 

[moinmoin]

The IO die will be mostly IO which by its very nature isn't conducive to shrinks as physical interfaces are hard to make smaller. For that matter, does GloFo support fan-out packaging on its advanced nodes? That's the only way I can see them offering a more featured IO die at less area.

 

[BorisTheBlade82]

We already know the IOD die size for Genoa is smaller than Rome/Milan, so it has to be 6nm.

According to the calculation that was done in the linked thread (proportions of IO vs. Logic, expected scaling, minor optimizations) it would not be entirely out of this world.
Also, SemiAnalysis seem to be quite sure that AMD will use Fan Out. But we don't know if they will use it for the CCD or the IOD. Intuition points to the latter. Of course one can argue that pad limitation would be an even bigger problem with a TSMC process.

IMHO the odds are still 60%:40% for 7/6nm, but 12LP GF is much more realistic than I initially thought.

 

[gdansk]

I suspect a mix
Consumer IOd on GF's new 12nm
Server IOd on TSMC 6nm

Or maybe the new 12nm IOd is really for some embedded products only.

 

[ryanjagtap]

IMHO the odds are still 60%:40% for 7/6nm, but 12LP GF is much more realistic than I initially thought.

12LP or 12LP+?

 

[Joe NYC]

I don't believe the difference is very large and 12LP+ comes with a density increase over 14 nm so that doesn't exclude the possibility of 12LP+ being used. I believe the IOD size will largely be set by the pad/bump count anyway so going to denser processes won't have much effect on die size unless they allow for tighter pad/bump pitches that AMD can utilize.

If the rumor that AMD is going with Fan Out, that would mean they can use micro-bumps.

Which is what would allow 6nm IOD to be substantially smaller than 14/12nm die.

 

[BorisTheBlade82]

12LP or 12LP+?

12LP+

 

[Mopetar]

I suspect a mix
Consumer IOd on GF's new 12nm
Server IOd on TSMC 6nm

More likely the other way around with server on 12nm GF and consumer on 6nm TSMC if anything uses that at all.

Rumors have suggested that the Zen 4 IO die will contain built in graphics and even if it's really minimalist, that logic would all benefit from a die shrink.

The server IO die is going to be massive no matter what and there's little reason to make large dies like that on TSMC wafers that are expensive and of limited quantity.

Even with a small GPU the consumer dies may still be GF since no one cares about the performance and the majority of the die is still PHY components that don't shrink well or at all.

Even with a move to 5nm for some products AMD can't afford to throw away 6nm wafers that can be used for GPUs or console APUs in a more valuable way than making an IO die. The GF process is said to have good power characteristics so even if it's not quite as good as a 7nm pet in that regard it will be in the same ballpark and at a much better price per unit.

 

[LightningZ71]

So, you're speculating that it could be a split where desktop Zen4/AM5 starts off with a TSMC N6 IOD, which could potentially leave enough package room for three N5 CCDs, and EPYC/TR Pro can use GF 12LP+? The question is, how does Gf produce an IOD that uses the interconnect layer that we are speculating for the CCDs (fan out). I can also see where there is a case for an N6 IOD for Bergamo that is on N6 instead of GF 12LP+ due to the target market (very high density racks) where every watt of power is crucial. An N6 IOD could potentially be physically small enough (assuming they can achieve the needed bump density) to have 16 CCDs on the package. This would mean that AMD doesn't have to produce 16 core CCDs to achieve 128 cores per package. Its just a lot of expense for a rather specific and tailored market...

 

[ryanjagtap]

12LP+

If they use 12LP+ which has upto 40% power reduction at ISO power from 12LP, and use the power management features they used in this image, they can reduce the amount of power the IO die consumes as a whole, right?

 

[moinmoin]

Its just a lot of expense for a rather specific and tailored market...

By all accounts Azure alone is likely already making it worth the effort.

 

[Mopetar]

I can also see where there is a case for an N6 IOD for Bergamo that is on N6 instead of GF 12LP+ due to the target market (very high density racks) where every watt of power is crucial. An N6 IOD could potentially be physically small enough (assuming they can achieve the needed bump density) to have 16 CCDs on the package.

You've made a mistake in assuming that an N6 IO die would be vastly smaller than the one made on an older GF nose. This isn't the case because the smaller transistors are wasted when the physical interconnects cannot be reduced in size and there's a limit to how tightly pins, etc. can be spaced. I believe you don't even get a power advantage because the smaller wires have a higher resistance that needs to be overcome so it offsets the usual performance gains when it comes to much of the hardware that's being placed on an IO die.

Maybe it makes financial sense for very niche markets, but AMD is so far ahead in server right now and likely to stay that way for the immediate future that there's little reason for them to go down that route.

 

[gdansk]

More likely the other way around with server on 12nm GF and consumer on 6nm TSMC if anything uses that at all.

Rumors have suggested that the Zen 4 IO die will contain built in graphics and even if it's really minimalist, that logic would all benefit from a die shrink.

The server IO die is going to be massive no matter what and there's little reason to make large dies like that on TSMC wafers that are expensive and of limited quantity.

Even with a small GPU the consumer dies may still be GF since no one cares about the performance and the majority of the die is still PHY components that don't shrink well or at all.

Even with a move to 5nm for some products AMD can't afford to throw away 6nm wafers that can be used for GPUs or console APUs in a more valuable way than making an IO die. The GF process is said to have good power characteristics so even if it's not quite as good as a 7nm pet in that regard it will be in the same ballpark and at a much better price per unit.

Ah, I totally forgot about the rumored GPU. Good point.

 

[LightningZ71]

I don't expect an N6 IOD to be significantly smaller than a conjectural 12lp+ one, however, shaving just 20% off of the dimensions would likely allow them to fit four total additional CCDs over a twelve CCD, 96 core solution (again, interconnect allowing, which I don't know). If they use hypothetical Zen4 CCDs that don't have AVX512, or use high density libraries as opposed to high performance ones, and are physically smaller than the ones from Genoa, then there's really no need.

Heck, maybe Nosta isn't on a controlled substance and GF 22FDX/12FDX really is the holy grail and they use that instead?

 

[eek2121]

Ah, I totally forgot about the rumored GPU. Good point.

The GPU only has 2 CUs according to leaks. That being said, I suspect they'll go with 6nm. Going with glofo IO dies would actually hurt them (in terms of flexibility, capacity, and cost) in the long run. Sticking to TSMC for everything would be the best approach.

I don't expect an N6 IOD to be significantly smaller than a conjectural 12lp+ one, however, shaving just 20% off of the dimensions would likely allow them to fit four total additional CCDs over a twelve CCD, 96 core solution (again, interconnect allowing, which I don't know). If they use hypothetical Zen4 CCDs that don't have AVX512, or use high density libraries as opposed to high performance ones, and are physically smaller than the ones from Genoa, then there's really no need.

Heck, maybe Nosta isn't on a controlled substance and GF 22FDX/12FDX really is the holy grail and they use that instead?

Nah, Nosta is definitely on controlled substances. 😂

 

[andermans]

The GPU only has 2 CUs according to leaks. That being said, I suspect they'll go with 6nm. Going with glofo IO dies would actually hurt them (in terms of flexibility, capacity, and cost) in the long run. Sticking to TSMC for everything would be the best approach.

At that size I think encoder/decoder/display capabilities are probably the main consumer of die space for the GPU.

 

[maddie]

The GPU only has 2 CUs according to leaks. That being said, I suspect they'll go with 6nm. Going with glofo IO dies would actually hurt them (in terms of flexibility, capacity, and cost) in the long run. Sticking to TSMC for everything would be the best approach.


Nah, Nosta is definitely on controlled substances. 😂

How in the world do you reason this?

At the rate they need silicon to continue rapid growth, using TSMC for everything will probably hurt them more. Don't forget that Nvidia is returning and Intel is also competing for the latest nodes. 33-40% of your silicon area for servers from GloFlo will help a lot. One of the big advantages of chiplets is to do precisely this sort of mixing to maximize marketshare & margins.

 

[NostaSeronx]

GF 22FDX/12FDX really is the holy grail and they use that instead?

Not primarily aimed for that.

22FDX/12FDX is aimed for sub-200 mm2 monolithic solutions or sub-150 mm2 advanced 2.5D/3D solutions; newest being 3D-MIV or 2.5D-Photonics both of which are slated for 2023+++.

Then, 22FDX is predominately aimed for small, cheap, monolithic chips like BRL&STR. Of which, AMD would max out cost-efficiency by inserting at the trailing edge;

Cadence Successfully Tapes Out Tensilica SoC on GLOBALFOUNDRIES 22FDX Platform Using Adaptive Body Bias Feature

Cadence announced that it has collaborated with GLOBALFOUNDRIES (GF) to successfully tape out a Cadence Tensilica test chip on GF’s 22FDX platform.

www.cadence.com

Still waiting for DesignWare I/O ABB from Synopsys and Cortex/Performance w/ ABB, Xtensa LX/NX w/ ABB, etc.

Given the time of 2017 <-> 2021+ for 22FDX ABB support, 12FDX's Bi-directional ABB would require more time to support. For example, lets say September-October 2022 for 12FDX, it wouldn't be till 2027 for insert given above ABB insert.

Given the above it is largely limited to AMD's price-orientated/mature-node series; Geode/Sempron/G-series.

Obligatory Fab expansion news:
Singapore 22FDX expansion set for 2023. (Fab 7 New Fab Module 1?&2!)
Dresden 22FDX/12FDX expansion set for 2024. (Module 3!&4?)
Expansion from Malta largely depends on GlobalWafers MEMC SOI fab of which can hit anywhere between 2022(now)-2025.

Unless they want to have really crippled Zen4-parts on AM5;
Single 64-bit DDR5
Single GMI thus only one CCD
No Integrated GFX, etc
Very H610 clone-esque? but a lot cheaper?

I don't see any FDX-node paired with anything Zen-node.

 

[Joe NYC]

The GPU only has 2 CUs according to leaks. That being said, I suspect they'll go with 6nm. Going with glofo IO dies would actually hurt them (in terms of flexibility, capacity, and cost) in the long run. Sticking to TSMC for everything would be the best approach.

Especially, considering future advanced packaging technologies, possibly including SoIC stacking.

 

[ryanjagtap]

Still waiting for DesignWare I/O ABB from Synopsys and Cortex/Performance w/ ABB, Xtensa LX/NX w/ ABB, etc.

Yeah, zen 4 needs ddr5, doesn't it? And 12LP+ and 22FDX don't have that yet.

On another matter, they are still using SERDES right, the fan-out is only for MI250.