Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[BorisTheBlade82]

Yeah, zen 4 needs ddr5, doesn't it? And 12LP+ and 22FDX don't have that yet.

On another matter, they are still using SERDES right, the fan-out is only for MI250.

Regarding Fan Out: https://semianalysis.substack.com/p/advanced-packaging-part-2-review

"SemiAnalysis can confirm that Zen 4 based desktop and server products will use a fan out. This fan out will then be packaged traditionally on top of a standard organic substrate which will have LGA pins on the bottom of this. The company packaging these products and technical reason for moving to fan out will be revealed behind the paywall."

 

[yuri69]

SemiAnalysis can confirm that Zen 4 based desktop and server products will use a fan out.

This is very cool. Especially Genoa's 12vs1 interconnects' power-efficiency should profit from this, right?

What about the price increase? AMD is most likely going to keep reusing the dies for server and desktop product lines so the fan out tech is likely gonna be used even in 1CCD + 1IOD Ryzen models.

There have already been complains regarding the lack of cheaper end of the 5000-seriers. Using this tech even for consumer products - unlike HPC accelerators and EPYCs - sounds weird.

Is the price not that high? Are they gonna use different chip packaging for the Ryzen line?

 

[Joe NYC]

This is very cool. Especially Genoa's 12vs1 interconnects' power-efficiency should profit from this, right?

What is the source of the power efficiency improvement?

Is the price not that high? Are they gonna use different chip packaging for the Ryzen line?

I have seen rumor that both are using it. The cost is going to be a factor...

 

[soresu]

This is very cool. Especially Genoa's 12vs1 interconnects' power-efficiency should profit from this, right?

What about the price increase? AMD is most likely going to keep reusing the dies for server and desktop product lines so the fan out tech is likely gonna be used even in 1CCD + 1IOD Ryzen models.

There have already been complains regarding the lack of cheaper end of the 5000-seriers. Using this tech even for consumer products - unlike HPC accelerators and EPYCs - sounds weird.

Is the price not that high? Are they gonna use different chip packaging for the Ryzen line?

The post you quoted says desktop and server.

Desktop = Ryzen.

 

[yuri69]

What is the source of the power efficiency improvement?

Using dense and short routing => less power required, better signal, etc. compared to the classic organic substrate.

The post you quoted says desktop and server.

Desktop = Ryzen.

Yea, my question was aimed towards economic viability of models such as a '7600X'.

 

[moinmoin]

This is very cool. Especially Genoa's 12vs1 interconnects' power-efficiency should profit from this, right?

What about the price increase? AMD is most likely going to keep reusing the dies for server and desktop product lines so the fan out tech is likely gonna be used even in 1CCD + 1IOD Ryzen models.

There have already been complains regarding the lack of cheaper end of the 5000-seriers. Using this tech even for consumer products - unlike HPC accelerators and EPYCs - sounds weird.

Is the price not that high? Are they gonna use different chip packaging for the Ryzen line?

The lower end desktop product range will be more and more covered by the mobile oriented APUs as it's already happening. Currently those are still monolithic, but there are not few voices expecting them to be moved to chiplets as well. If so you're right that such then need to be economically viable even at low prices.

 

[BorisTheBlade82]

Using dense and short routing => less power required, better signal, etc. compared to the classic organic substrate.

As I understand it the routing will basically stay the same. The Fan Out is only to prevent pad limitation. So to my admittedly limited knowledge there should be no significant gain in power efficiency.

 

[MadRat]

So is fan out for use on an interposer or to attach to the final packaging?

 

[Tuna-Fish]

As I understand it the routing will basically stay the same. The Fan Out is only to prevent pad limitation. So to my admittedly limited knowledge there should be no significant gain in power efficiency.

If they use the fanout packaging between the IOD and the CCD, this will greatly reduce the capacitance for the path between them. ( = reduce power)

 

[jpiniero]

The lower end desktop product range will be more and more covered by the mobile oriented APUs as it's already happening. Currently those are still monolithic, but there are not few voices expecting them to be moved to chiplets as well. If so you're right that such then need to be economically viable even at low prices.

Or they just won't sell low end products. If they were able to separate out the IGP and have it be from a different node, that would save a ton of leading edge wafers.

 

[moinmoin]

Or they just won't sell low end products.

I think there being enough supply for low end products to be worth selling (i.e. the demand of all higher end products is being fulfilled already) is a clear prerequisite. Of course right now we are far off such a market situation.

 

[BorisTheBlade82]

If they use the fanout packaging between the IOD and the CCD, this will greatly reduce the capacitance for the path between them. ( = reduce power)

Maybe I am misunderstanding the terms but to my understanding it is the following:
Fanout is just a technology to adapt a high density bump pitch (die) to a lower density bump pitch (package, interposer, etc.). As I said, just to prevent pad limitation.
It depends on what you connect to the fanout. If it is the same old organic package then power efficiency won't change. But you could also connect it to an interposer, LSI, EFB, EMIB, etc. This of course would improve power efficiency. But from everything we know I think it will still be the organic package.
If I am wrong please feel free to correct me.

 

[moinmoin]

Genoa has a game-changing tech under the hood

That's all of Charlie's teaser this time. Shortest teaser evar?

Genoa has a game-changing tech under the hood

AMD’s upcoming Genoa CPU has a feature SemiAccurate thinks will change the game.

semiaccurate.com

 

[Mopetar]

The GPU only has 2 CUs according to leaks. That being said, I suspect they'll go with 6nm. Going with glofo IO dies would actually hurt them (in terms of flexibility, capacity, and cost) in the long run. Sticking to TSMC for everything would be the best approach.

Moving everything to TSMC really cuts in to how much they can produce and in a market where AMD has the best products that's far worse than making a marginally better product.

There are limits to how much an IO die can shrink and these are large chips, especially for their server parts.

It also ignores all of the AMD commitments to buy wafers from GF that they've agreed to (and recently expanded) with Global Foundries.

Especially, considering future advanced packaging technologies, possibly including SoIC stacking.

There isn't a lot that can be stacked on an IO die and even if you could drop a massive L4 cache layer on top of it, why do that instead of stacking additional cache on the Zen chiplets? The added latency of having to go to the IO die for that cache is going to limit the actual performance gains it can achieve. Zen 3D has shown us that the set of applications that benefit most from the larger cache are limited, so how much an L4 adds outside of niche uses is questionable.

 

[moinmoin]

Genoa has a game-changing tech under the hood

That's all of Charlie's teaser this time. Shortest teaser evar?

Genoa has a game-changing tech under the hood

AMD’s upcoming Genoa CPU has a feature SemiAccurate thinks will change the game.

semiaccurate.com

Somebody hinted that it's something that Genoa introduces and Intel won't have until Granite Rapids. Looking around it seems GNR introduces Rambo Cache from Xe-HPC, to which the AMD counterpart would be Infinity Cache.

 

[ahimsa42]

no mention of Phoenix so is it safe to assume mobile zen4 won't be released until 2023?

AMD Reaffirms Radeon RX 7000 'RDNA 3' GPUs & Ryzen 7000 'Zen 4' CPU Launch In 2022, Spending Big Money To Secure Increased Capacity

AMD's CEO reaffirmed that both the next-gen Radeon RX 7000 'RDNA 3' GPUs and Ryzen 7000 'Zen 4' CPUs will launch this year.

wccftech.com

 

[moinmoin]

no mention of Phoenix so is it safe to assume mobile zen4 won't be released until 2023?

AMD refreshes its mobile products at the beginning of every new year.

 

[Joe NYC]

It also ignores all of the AMD commitments to buy wafers from GF that they've agreed to (and recently expanded) with Global Foundries.

Milan will continue to soak up this capacity, at increasing pace.

There isn't a lot that can be stacked on an IO die and even if you could drop a massive L4 cache layer on top of it, why do that instead of stacking additional cache on the Zen chiplets? The added latency of having to go to the IO die for that cache is going to limit the actual performance gains it can achieve. Zen 3D has shown us that the set of applications that benefit most from the larger cache are limited, so how much an L4 adds outside of niche uses is questionable.

There is a lot of talk about Active Silicon Bridges - related to RDNA3 - which could be stacked.

If this technology makes it to the future generations of Zen, the connection between CCD and IOD could be stacked active silicon bridge. And for that, TSMC N6 based IOD would be needed.

And from Charlie's article, A LOT of stacked L3 will be needed in the upcoming server processors.

 

[Hans Gruber]

AMD should push up their Zen 4 release date. They are giving Intel way too much time for a secondary strike. Let's assume that Zen 4 is a great CPU with huge IPC improvements over Zen 3. Then Intel responds with something beyond Zen 4 by the end of the year that is 10-15% better than Zen 4? What would AMD do?

The sooner AMD releases Zen 4, the more time they have to sell the CPU before Intel can respond with something better.

I look at CPU prices for Alder Lake and cannot figure out what AMD is thinking.

 

[jpiniero]

AMD should push up their Zen 4 release date. They are giving Intel way too much time for a secondary strike. Let's assume that Zen 4 is a great CPU with huge IPC improvements over Zen 3. Then Intel responds with something beyond Zen 4 by the end of the year that is 10-15% better than Zen 4? What would AMD do?

The sooner AMD releases Zen 4, the more time they have to sell the CPU before Intel can respond with something better.

I look at CPU prices for Alder Lake and cannot figure out what AMD is thinking.

They are too busy counting the money they are making from Genoa.

 

[biostud]

AMD should push up their Zen 4 release date. They are giving Intel way too much time for a secondary strike. Let's assume that Zen 4 is a great CPU with huge IPC improvements over Zen 3. Then Intel responds with something beyond Zen 4 by the end of the year that is 10-15% better than Zen 4? What would AMD do?

Release 6800X3D?

And RK-L is still Intel-7, like AD-L which just pulled ahead of zen3, using a lot more power under full load. They will have to go up against TSMC 5nm. If they somehow beat zen4 in raw performance, it's going to cost on the power consumption.

 

[Saylick]

Somebody hinted that it's something that Genoa introduces and Intel won't have until Granite Rapids. Looking around it seems GNR introduces Rambo Cache from Xe-HPC, to which the AMD counterpart would be Infinity Cache.

Does Sapphire Rapids support CXL?

 

[moinmoin]

Does Sapphire Rapids support CXL?

Yes

 

[Exist50]

Does Sapphire Rapids support CXL?

Kinda. Doesn't support CXL.mem, so AMD will probably be first to that. Which is really embarrassing for Intel, having invented it and all.

 

[Saylick]

Yes

So if that's ruled out, then I agree with you. Maybe we'll see >1 layer of V-cache on some of the SKUs.