Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[eek2121]

It actually does beat 8C Zen3 in said compilation tests in Phoronix testing:

View attachment 57517


Lowly 12400 with 4.4Ghz turbo clocks and 18MB of L3 has no trouble keeping up with premier AMD 8C cpu with 32MB of L3.

People keep conveniently forgetting that ADL big core is 5 ALU (each LEA capable), 512 ROB, mostly 6-wide monster. It is let down currently by mobile phone worthy uncore and memory controller, but expect it to scale real well in the future with faster mem.

The only "complex" benchmark i need is Web Speedometer 2.0 (thread is in on this very forum). Since i own 10900K, 5950X and 12900K, the numbers with 3800-3900 HIGHLY tuned DDR4 are the following ~210, ~255 and 330. That's how faster and more smooth ADL is. I believe 12900K does like 300 on stock as well. ~25% faster in my eyes.

It ran at 5.6 ghz, not 4.4 ghz? Processor: Intel Core i5-12400 @ 5.60GHz

EDIT: Just saw mods post. Not commenting further in this thread.

 

[gruffi]

The rumors surrounding Zen 4's IPC obviously don't specify whether it's an average or a range.

Usually rumors are never a meaningful average. They can be an indicator. That's all. So, always take it with a grain of salt.

Spoiler

I said "in several workloads," not across the board. Those workloads are predominantly CPU limited games, single threaded applications, code compiling and encoding. When I was looking at the reviews, those workloads stood out to me as great representations of Golden Cove's performance advantage over Zen 3.

Who cares about cherry picking? There are also workloads where Golden Cove has lower IPC than Zen 3. It would only be impressive if it was a win on all fronts. But it isn't. It clearly has some weaknesses, like latency. Which results in some losses against Zen 3 and even 11th gen. Even the 8-thread Zambezi Bulldozer had its highlights when it could compete against 12-thread 980X in some apps like V-Ray. While it clearly lost against 8-thread Sandy Bridge overall. Zen 3 also had amazing performance uplifts "in several workloads". Overall Golden Cove has similar IPC uplift as Zen 3. But the latter is more impressive to me because it was done on the same 7nm process as Zen 2 without increasing power consumption. And it was released before 11th gen which couldn't beat Zen 3. Golden Cove is one year newer than Zen 3. In fact it should have some advantages over Zen 3. Otherwise it would have been another disappointment as 11th gen. Actually it's absolutely outstanding what AMD did with Zen 3. Which raises the bar for Zen 4 and 5, of course. But I'm sure AMD won't slow down, continuing the progress they made with Zen 2 and 3.

 

[ryanjagtap]

Does anyone think that the 170W TDP rumor may be the power limit of AM5 socket as a whole instead of being a single ryzen processor with that much rated TDP?
We already heard that AMD is raising TDP for zen 4, but with them still using the same node/design throughout the product stack for desktop/HEDT/data center as well as their commitment of 30x energy effeciency in AI and data center by 2025, 170W TDP for a desktop chip seems too high.

 

[DrMrLordX]

Remains to be seen how good Zen4 can do.

According to the few people who have seen it in action, very very well. Of course we won't get any good leaks unless maybe someone snags a stray Genoa off a Chinese marketplace.

Does anyone think that the 170W TDP rumor may be the power limit of AM5 socket as a whole instead of being a single ryzen processor with that much rated TDP?

What else would be drawing power through the socket?

 

[RnR_au]

Does anyone think that the 170W TDP rumor may be the power limit of AM5 socket as a whole instead of being a single ryzen processor with that much rated TDP?

There is already a rumour about a cpu drawing close to that much power.

https://twitter.com/x/status/1493120743978283016

 

[moinmoin]

There is already a rumour about a cpu drawing close to that much power.

https://twitter.com/x/status/1493120743978283016

Hm, so 170W TDP or 170W PPT? With the current rules 162W PPT would be ~118W TDP.

 

[eek2121]

Hm, so 170W TDP or 170W PPT? With the current rules 162W PPT would be ~118W TDP.

Could actually be 125W. Current Ryzen is 105W TDP/142W PPT, add 20W to both and you get 125W/162W.

 

[Joe NYC]

Apparently, Bergamo will be a performance monster:

How well does AMD's Bergamo CPU perform? - SemiAccurate

 

[moinmoin]

Could actually be 125W. Current Ryzen is 105W TDP/142W PPT, add 20W to both and you get 125W/162W.

PPT had been defined as TDP * 1.35 before. So to correct myself, 162W PPT should be 120W TDP.

 

[DisEnchantment]

https://twitter.com/x/status/1415254514677043205

https://twitter.com/x/status/1415262170623905795

65, 95, 105, 120 and 170 W.

PPT would be 88W, 128W, 142W, 162W, 229W.
Up to 229W PPT/170W TDP on AM5

 

[LightningZ71]

229/170W? That sounds like enough power to support three CCD chiplets on one package....

 

[coercitiv]

Careful with assigning a formula for TDP > PPT conversion. Remember the 5600X is 65W TDP and yet peak power stays within 76W at stock. It's ok to expect a PPT limit around 135% TDP, but it can always vary based on AMDs decision. (within reason ofc)

For example I would expect a CPU that comes with a stock cooler to aim at a lower multiplier for PPT limit, while a flagship CPU aiming for the "crown" may take more liberties based on expected (enthusiast) cooling and AM5 limits.

 

[soresu]

229/170W? That sounds like enough power to support three CCD chiplets on one package....

More like 4 CCD's.

They are AM5 limits, not Zen4 AM5 limits I'd wager.

 

[LightningZ71]

Makes sense that it would be socket limits. If we consider that the IoD will consume about 20watts (it'll have a iGPU to feed now, even if its on an improved process), and we consider that each CCD can pull 50watts on its own, then 170 watts covers that nicely for three CCDs and an IoD. The communications paths between the chiplets also eats a bit of power, so, a three CCD package will be rather power hungry at full tilt. I don't see how you get a CCD package to work unless you take the N3 density improvements without increasing transistor count and also do your best to shrink the IoD as much as possible.

 

[moinmoin]

Careful with assigning a formula for TDP > PPT conversion. Remember the 5600X is 65W TDP and yet peak power stays within 76W at stock. It's ok to expect a PPT limit around 135% TDP, but it can always vary based on AMDs decision. (within reason ofc)

Is there a known case of PPT being higher than TDP * 1.35? It being lower is not really interesting as that just adds headroom.

 

[coercitiv]

Is there a known case of PPT being higher than TDP * 1.35? It being lower is not really interesting as that just adds headroom.

Stricly speaking, PPT being higher or lower doesn't add or remove headroom, the cooling solution is the one that adds or removes headroom.

But no, I know of no AMD CPU with higher TDP/PPT ratio. I can however point you towards Intel's PL1/PL2 ratio. Long time ago, in a galaxy far away, Intel liked using a PL2 = 1.25X PL1 ratio. They did so for half a decade.

Spoiler

But then the going got though and they pushed and pushed that PL2 until we got quite close to PL2 = 2X PL1. They don't even call it TDP anymore

 

[DrMrLordX]

If AMD is going to release 3 and 4 CCD products on AM5, will there be any future for Threadripper outside of maybe Threadripper Pro?

 

[Hitman928]

If AMD is going to release 3 and 4 CCD products on AM5, will there be any future for Threadripper outside of maybe Threadripper Pro?

It looks like Threadripper Pro only going forward, but that's just my take.

 

[Joe NYC]

If AMD is going to release 3 and 4 CCD products on AM5, will there be any future for Threadripper outside of maybe Threadripper Pro?

There are some rumors of small Genoa Socket SP6 with 4 memory channels. That could be a good sweet spot for Threadripper

 

[moinmoin]

Stricly speaking, PPT being higher or lower doesn't add or remove headroom, the cooling solution is the one that adds or removes headroom.

My point is rather if e.g. a board supports chips with a TDP of 65W it's with a PPT of 88W. A particular chip using just 76W PPT is then within the spec. A chip going beyond TDP * 1.35 wouldn't.

As for Intel's PL1/PL2 shenanigans AMD does have a counterpart in its mobile chips with no definite names (short and long term boost or something) though on my 4500U they don't really add anything beyond stock and rather appear to be used for temperature/power usage throttling.

If AMD is going to release 3 and 4 CCD products on AM5, will there be any future for Threadripper outside of maybe Threadripper Pro?

Charlie teased about a smaller Epyc socket(?) which could also be used for Threadripper. But HEDT as a separate platform appears to be effectively dead outside of workstation.

 

[dnavas]

Charlie teased about a smaller Epyc socket(?) which could also be used for Threadripper. But HEDT as a separate platform appears to be effectively dead outside of workstation.

Pretty disappointing if true, but I guess the writing was on the wall as soon as they let us know that TR was an engineering-led effort.

 

[moinmoin]

Pretty disappointing if true, but I guess the writing was on the wall as soon as they let us know that TR was an engineering-led effort.

I guess for AMD the writing was rather how Intel handles HEDT (or rather how it let that market implode after it wasn't competitive anymore against TR). AMD seems most interested in gaining profitable shares in existing sizable markets, HEDT appears not to be one anymore.

 

[soresu]

If AMD is going to release 3 and 4 CCD products on AM5, will there be any future for Threadripper outside of maybe Threadripper Pro?

It looks like Threadripper Pro only going forward, but that's just my take.

TR Pro is the absolute top end of the AMD consumer CPU product stack with more PCIe lanes and memory channels than 99.9% of consumers need.

It's the equivalent of the old multi GPU SLI/Crossfire market when that was still popular vs its reduced state now (MCM GPU designs may revive that on a single board level).

4 CCD is still just 32C maximum until CCD's increase to 16C each, which IMHO won't happen until at least Zen6 for consumer products, if ever.

If Epyc increases to 96 and 128C that means TR will follow - leaving the same current 4:1 ratio of core counts from high end/enthusiast halo to mainstream desktop SKUs.

 

[coercitiv]

My point is rather if e.g. a board supports chips with a TDP of 65W it's with a PPT of 88W. A particular chip using just 76W PPT is then within the spec. A chip going beyond TDP * 1.35 wouldn't.

I can't really follow you. Whether an AM4 board is within spec or not has little to do with the choices manufacturers will make with AM5 boards and the new power limits AMD defines for the socket.

My original point was very simple: there is no rule that PPT must be 1.35X TDP for AM5 (unless that old Gigabyte leak contained PPT limits as well). Going 20-40% over TDP is a very good idea in the sense that it makes sense from a cooling perspective, but AMD may still have decided to follow Intel through the rabbit hole. Part of me wants AMD to stay true to their much saner approach, the other part wants to see a final showdown that exposes just how stupid this marketing game was to begin with.

 

[moinmoin]

My original point was very simple: there is no rule that PPT must be 1.35X TDP for AM5

Part of me wants AMD to stay true to their much saner approach, the other part wants to see a final showdown that exposes just how stupid this marketing game was to begin with.

I'm assuming AMD stays true to their much saner approach (usual disclaimer about "ass-u-me" applies).