Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Mopetar]

Those EUV machines aren't cheap. Even before the hikes they can justify keeping pricing the same or more because of the density increase.

AMD will be fine as long as they can pass on the extra costs.

Nothing is free, but it's always a question of maximizing profit. Just like companies often lower prices in order to increase sales volume, the same can be applied here. If N6 allows significantly more throughput and there are a lot of customers still on N7, it may be worth TSCM's while to offer some incentive to move to N6. Any logic that applies to increasing prices on N7 applies even more so for N6, but it doesn't matter if both go up and the relative difference remains the same. Anyone with an existing N7 design isn't going to get a density increase unless they change the design and that's extra cost, so from their perspective the only gain from moving to N6 is performance increase due to better power/frequency characteristics. Nice, but not necessarily worth a new set of masks. If the wafers are cheaper then with enough wafers the new masks pay for themselves.

The sooner they can move everyone to N6, the more time to ROI on those EUV machines before even the N6 node becomes several generations old and has prices lowered. You could even make a better argument for offering lower prices initially to get everything moved over to N6 and then raising prices afterwards. Then they get higher prices on top of higher volumes. One way or another, TSMC should want to get everyone off of N7. Whether that's getting N7 products moved to N5 or N6 doesn't matter, just as long as they can transition all of their N7 production to N6 as quickly as possible. The only real limiting factor is the rate at which they can get the EUV equipment to do so.

 

[SteinFG]

The interesting thing about this recent genoa shot is the different color of io and chiplets (golden reflection vs black reflection). So there is a little bit of hopium left in me for some fan-out tech being used on the io die. But i'm not sure anymore, seeing that almost everything is doubled in genoa iod (1.5x ram banwidth, 1.5x ram slots, 2x pcie banwidth, 1.5x chiplet connections), I won't be surprised if there's no new packaging techniques.

Edit: don't know if anyone mentioned but semianalysis changed their info some days ago about amd's packaging (Pic), so there's even less hope for cool stuff

 

[eek2121]

Nothing is free, but it's always a question of maximizing profit. Just like companies often lower prices in order to increase sales volume, the same can be applied here. If N6 allows significantly more throughput and there are a lot of customers still on N7, it may be worth TSCM's while to offer some incentive to move to N6. Any logic that applies to increasing prices on N7 applies even more so for N6, but it doesn't matter if both go up and the relative difference remains the same. Anyone with an existing N7 design isn't going to get a density increase unless they change the design and that's extra cost, so from their perspective the only gain from moving to N6 is performance increase due to better power/frequency characteristics. Nice, but not necessarily worth a new set of masks. If the wafers are cheaper then with enough wafers the new masks pay for themselves.

The sooner they can move everyone to N6, the more time to ROI on those EUV machines before even the N6 node becomes several generations old and has prices lowered. You could even make a better argument for offering lower prices initially to get everything moved over to N6 and then raising prices afterwards. Then they get higher prices on top of higher volumes. One way or another, TSMC should want to get everyone off of N7. Whether that's getting N7 products moved to N5 or N6 doesn't matter, just as long as they can transition all of their N7 production to N6 as quickly as possible. The only real limiting factor is the rate at which they can get the EUV equipment to do so.

I think what a few people here don't understand is the biggest cost for making chips isn't the cost of the machines themselves, it is the total machine time used per wafer. That is why TSMC charges less for 6nm. You can make more chips with 6nm (due to increased density) vs. 7nm and make them quicker thanks to EUV.

 

[RnR_au]

N5 is higher yielding than N7. Whatever bad dies they do you can be certain are getting thrown at EPYC first if anywhere, in particular for the eventual F SKUs.

I was under the impression that EPYC got the best dies?

 

[Markfw]

I was under the impression that EPYC got the best dies?

Not sure how you define best. The ones that clock lower, but use less voltage I would think go to EPYC. But that kind of excludes desktop, which ALL clock higher than EPYC.

 

[RnR_au]

Not sure how you define best. The ones that clock lower, but use less voltage I would think go to EPYC. But that kind of excludes desktop, which ALL clock higher than EPYC.

Lowest leakage? But yeah, not sure.

Edit: threw TechTechPotato a tweet with the question

https://twitter.com/x/status/1513299975442411522

 

[Thala]

I was under the impression that EPYC got the best dies?

Depends on what is considered best? Typically the slow dies having the best power characteristics, so those will most likely be binned for EPYC.
I also assume the design is validated against the SS (slow slow) corner with the frequencies required for EPYC.

 

[MadRat]

96-Core Processor Made of Chiplets

CEA-Leti bound dozens of processor cores together by breaking them up and stitching them back together on a separate piece of silicon

spectrum.ieee.org

View attachment 59812

That's thick too and doesn't look fake.

Sure looks like an interposer with chiplet cores. But could it also be the wrong notion and instead it be cache chiplets on top of monolithic cores? AMD could conceivably be paring core groupings to segment their markets. Larger cores could be cut with more core segments than smaller cores. What we may be looking at could be a core cut out of a larger grid to make a 2x3 core each with 4 or 8 cores in each grid block. Cache is then tied to each grid block. Server parts would simply contain more grid blocks over consumer devices. The communication fabric between cores would be much faster this way than using an interposer.

 

[nicalandia]

96-Core Processor Made of Chiplets

CEA-Leti bound dozens of processor cores together by breaking them up and stitching them back together on a separate piece of silicon

spectrum.ieee.org

That's thick too and doesn't look fake.

That CPU pictured there is a TSARLET a prototype designed by CEA-Leti. It's built on 28nm.

TSARLET - Microarchitectures - CEA Leti - WikiChip

TSARLET was a research microarchitecture designed by CEA-Leti demonstarting the theoretical capabilities of a large-scale high-performance 3D stacked chiplets-based SoC technology. The project comprised 96 MIPS cores built using 6 chiplets 3D stack on an active interposer in order to demonstarte...

en.wikichip.org

From the Gigabyte Leak, we learn that each chiplet is less than 1 mm thick.

 

[RnR_au]

Edit: threw TechTechPotato a tweet with the question

He responded! He *is* a nice guy

https://twitter.com/x/status/1513479024756023299

Meanwhile, it seems AMD has a kickarse IMC...

https://twitter.com/x/status/1513934438836674560

 

[Abwx]

He responded! He *is* a nice guy

https://twitter.com/x/status/1513479024756023299

Meanwhile, it seems AMD has a kickarse IMC...

https://twitter.com/x/status/1513934438836674560

The quote from AMD rep doesnt specify what s the overclocked parameter :

Our first DDR5 platform for gaming is our Raphael platform and one of the awesome things about Raphael is that we are really gonna try to make a big splash with overclocking and I'll just kinda leave it there but speeds that you maybe thought couldn't be possible, maybe possible with this overclocking spec.
Joseph Tao, Memory Enabling Manager at AMD

AMD on Ryzen 7000 Zen 4 Desktop CPUs: Raphael, Our First DDR5 Gaming Platform, Is Going To Make A Big Splash With Overclocking

AMD has said that its Raphael Ryzen 7000 Desktop CPUs with Zen 4 gaming platform will make a big splash in overclocking.

wccftech.com

 

[CakeMonster]

Memory OC speaks well for the longevity of getting a Z4, that's good if it proves true.

 

[nicalandia]

We all know they are going to OC High since they showed an Octa Core running at 5 Ghz on All cores while gaming...! I suspect that the top of the line will reach 5.7 Ghz(boost)

 

[eek2121]

We all know they are going to OC High since they showed an Octa Core running at 5 Ghz on All cores while gaming...! I suspect that the top of the line will reach 5.7 Ghz(boost)

Doubtful. Remember there are many more transistors packed in together vs. Zen 3. I do think we will see 5+ ghz in many workloads, but I don’t believe it will happen with all of them (especially AVX), and unless AMD has performed some type of ritual sacrifice, I don’t think we will see single core clocks above 5.1-5.3 ghz.

 

[nicalandia]

I don’t think we will see single core clocks above 5.1-5.3 ghz.

5950X boosted past 5 Ghz on day one release. B2 stepping are boosting to 5.1 or more. Zen4 is going to surprise many people

 

[DrMrLordX]

Zen4 is going to surprise many people

Maybe more with the all-core clocks than anything else. I don't expect the single-core boost to go THAT high.

 

[moinmoin]

I'm honestly surprised as is that there's still room to raise the frequency. I was expecting the increase in performance to be much more down to IPC improvements than it has been the case in the last couple years.

 

[DrMrLordX]

I'm honestly surprised as is that there's still room to raise the frequency. I was expecting the increase in performance to be much more down to IPC improvements than it has been the case in the last couple years.

AMD shocked me with the single-core boost jump from Zen2 -> Zen3. Same process, but 400+ MHz jump? That was unexpected. Kinda why I have muted expectations for Zen4.

 

[Saylick]

There was a Chiphell post about how Zen 4 core had more pipeline stages to facilitate higher clocks... will need to dig it up. Hold on.

Edit: Found it. https://www.chiphell.com/thread-2404223-1-10.html Take with a grain of salt.

Zen4 has further improved in Branch Misprediction,
and increased L2 cache by the way, reducing the penalty caused by prediction errors, boldly lengthening
the pipeline, longer pipeline can bring higher CPU clock, AM5 is designed to be full .

 

[nicalandia]

I'm honestly surprised as is that there's still room to raise the frequency. I was expecting the increase in performance to be much more down to IPC improvements than it has been the case in the last couple years.

IPC wise it will be 20% or so. Total Performance will be Off the Chart due to IPC + Speed + DDR5.

 

[nicalandia]

There was a Chiphell post about how Zen 4 core had more pipeline stages to facilitate higher clocks... will need to dig it up. Hold on.

The High Clock is due entirely on TSMC High Performance 5nm process. Zen4 is an evolution of Zen3. Zen5 is where a entirely new uArch is expected

 

[andermans]

IPC wise it will be 20% or so. Total Performance will be Off the Chart due to IPC + Speed + DDR5.

Typically DDR5 effects would already be included in IPC, since it purely affects the number of instructions you will execute per cycle.

 

[deasd]

There was a Chiphell post about how Zen 4 core had more pipeline stages to facilitate higher clocks... will need to dig it up. Hold on.

Edit: Found it. https://www.chiphell.com/thread-2404223-1-10.html Take with a grain of salt.

Again chiphell... and It's the same guy that said Zen4 to be released in April. Urgh,,,.. and wtf they were talking about some negative content against Ukraine?? no thanks...

 

[thigobr]

Let's see what magic they did to overcome Fabric clock limitations and latency when running async/higher clocks... Current IO die is very limited past 1900MHz and with DDR5 clocking higher if they didn't do a good work Zen4 will take a latency hit when aiming higher memory frequencies.

 

[nicalandia]

Let's see what magic they did to overcome Fabric clock limitations and latency when running async/higher clocks... Current IO die is very limited past 1900MHz and with DDR5 clocking higher if they didn't do a good work Zen4 will take a latency hit when aiming higher memory frequencies.

They have Beefed Up the Zen4 IO die(at least in EPYC, Raphael will be a SOC)

Details on the Gigabyte Leak

Recently, a ransomware group leaked data from Gigabyte in an attempt to extort payment. That’s been well covered by other outlets (please everyone, secure your networks), so here we’re …

chipsandcheese.com