Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Abwx]

Psh, you think you're impatient? We really impatient people are already not waiting for Zen 5. Scrap Zen 4, we demand Zen 5 in 2022

Some expectations for Zen 5, albeit nothing is known about Zen 4...

Leak suggests AMD Zen 5 CPUs to pack impressive IPC performance gains and hugely increased core counts

RedGamingTech has leaked some early AMD Zen 5 info. The leak suggests Zen 5 chips will come with a hybrid design similar to Intel Alder Lake CPUs and will pack impressive gen-on-gen IPC performance gains.

www.notebookcheck.net

 

[xilli_fiberbit]

AMD call it EFB now :

ASE Technology and its affiliated Siliconware Precision Industries (SPIL) have also moved to volume produce AMD's new HPC chips for server applications, using their FOEB (fan-out embedded bridge) technology, which is similar to TSMC's InFO_S

https://twitter.com/x/status/1516672191508754435

 

[NostaSeronx]

This post is purely speculation: Derived from Genoa -> Bergamo -> Untitled 4th Gen EPYC 7004X/3004X 3D V-cache series from linkedin.

Zen4 X3D on EPYC V3D and Ryzen V3D has no on-die cache and,

Zen3 X3D/V3D = 2 TB/s, 64 MB L3D
Zen4 X3D/V3D = 4 TB/s, 128 MB L3D

The rumors from before are likely incorrect, all of the processors are likely under the L3D this time.

Zen4 -> Zen4c = +HPC Cells
while
Zen4/Zen4c -> Zen4x = +UHD Cells, -HPC Cells

Tracks:
8T - High Performance 3-Fin
6T - High Density 2-Fin
5T - Ultra High Density 1-Fin

HPC does not use 8T, but rather increases the metal width and metal pins of the 2-Fin Track from Mx=32nm to 36nm or something. With the pin count increase for a 6T cell slightly enlarging the cell, but no where near using 8T 3-Fin.
UHD does use 5T, not 100% certain if it will use HPC cells being a 3rd iteration of Zen4 on 5nm. Linear progression of Zen4 -> Zen4c -> Zen4x or split progression with Zen4 splitting into higher performance Zen4c(higher logic area budget) and lower leakage Zen4x(lower logic area budget).

12 CCDs w/ 16C and 4-Hi L3D = 192-cores + 6 GB of L3

Where as the Ryzen/EPYC Value Workstation w/ 4-Hi L3D = 32-cores + 1 GB of L3

By the way, there is an indication of a 16-core Zen3+ X3D product for Ryzen Pro on AM4.
Zen3-X3D before Raphael, Zen3+-X3D after Raphael, Zen4x-X3D after Granite Ridge.

X3D has a longer refresh cycle since it can increase performance(reduction of DRAM +100 cycle transfers for increase of Stacked SRAM +4*x cycle transfers) by stacking cache.
Gen1 96 MB -> Gen1.1 160 MB -> Gen1.2 288 MB -> Gen2 256MB -> Gen2.1 512MB, etc.

Zen3 = 3x to 9x scale
Zen4 = 4x to 16x+ scale

Guesswork:

MISC	MISC	MISC	MISC	MISC	MISC	MISC
Core 0	Core 1	L2S+L3I​	MISC​	L3I+L2S​	Core 8	Core 9
Core 2	Core 3	L2S+L3I​	MISC​	L3I+L2S​	Core 10	Core 11
Core 4	Core 5	L2S+L3I​	MISC​	L3I+L2S​	Core 12	Core 13
Core 6	Core 7	L2S+L3I​	MISC​	L3I+L2S​	Core 14	Core 15

This is not accurate in any way, just for example purposes(mainly because memory shrink calculation is awful):
With the over-generalized 2xZen4x floorplan following the 28nm Jaguar's CPU1/CPU2 with FPUs facing each other.

The above is just general shape to expect. 8x 2 MB L2 connected to 16x cores, etc. However, I expect the TSV placement to be fully centered.

SRAM Group A/B​

Interface+Interface​

SRAM Group A/B​

rather than

SRAM Group A​

Interface​

SRAM Group B​

SRAM Group A​

Interface​

SRAM Group B​

Using the 2X bandwidth from X3D on N5 to sub-channel both cores in cluster.

Extending backwards guessing on Zen4c: (Zen4[2x density] = 0.75 on both X/Y, Zen4c[<2x density] = >0.75(used 0.8) on both X/Y, Zen4x[>2x density] = <0.75 on both X/Y)

The L2/L3 cache should be shrinked on 0.86x on X and 0.86x on Y. So, just note that both of those sections would be smaller as well.

 

[eek2121]

Still, AMD is wafer limited at TSMC. TSMC just can't keep up with demand for it's top customers on leading edge nodes (not enough EUV supply from ASML and it's vendors, for example).

They could always port the design to Intel 4. 😈

Even more nuts when you factor in the possibility that even with a very optimistic 30% IPC uplift, Zen 4 may not be able to match the 5800X3D in MSFS, let alone beat it. Higher DDR5 speeds might help narrow the gap or even overcome it.

AMD is cooking up something special for DDR5. It is very likely Zen 4 is going to be the best gaming chip out there.

 

[DrMrLordX]

They could always port the design to Intel 4. 😈

LOL Intel 4's wafers are probably booked solid for awhile, considering how few of them there will be.

 

[nicalandia]

Impressive and very technical sound speculation

If AMD Adopted OMI in their EPYC Architecture

If AMD Adopted OMI in their EPYC Architecture - Download as a PDF or view online for free

www.slideshare.net

 

[moinmoin]

View attachment 60423

For those unaware, OMI stands for open memory interface:

About the Open Memory Interface (OMI)

OMI is a highly tuned bus that was developed for near memory and is easily migratable to emerging memory solutions (e.g., Storage Class Memory). This serial coherent bus, a subset of OpenCAPI, was architected specifically for the interface between a processor and Near Memory having absolute...

openmemoryinterface.org

Specification​	LRDIMM DDR4​	DDR5​	HBM2E(8-High)​	OMI​
Protocol​	Parallel​	Parallel​	Parallel​	Serial​
Signalling​	Single-Ended​	Single-Ended​	Single-Ended​	Differential​
I/O Type​	Duplex​	Duplex​	Simplex​	Simplex​
Paths/Channel (Read/Write)​	64​	32​	512R/512W​	8R/8W​
Data Transfer Rate​	3,200MT/s​	6,400MT/s​	3,200MT/s​	32,000MT/s​
Channel Bandwidth (R+W)​	25.6Gbytes/s​	25.6Gbytes/s​	400Gbytes/s​	64Gbytes/s​
Latency​	41.5ns​	​	60.4ns​	45.5ns​
Channels / Processor Die​	8 (EPYC Rome IO)​	​	5 (NVidia Ampere)​	16 (POWER10)​
Processor Die Size​	416mm²​	​	826mm²​	602mm²​
Driver Area / Channel​	7.8mm²​	3.9mm²​	11.4mm²​	2.2mm²​
Bandwidth / mm²​	3.3GBytes/s/mm²​	6.6GBytes/s/mm²​	35GBytes/s/mm²​	29.6GBytes/s/mm²​
Max Capacity / Channel​	64GB​	256GB​	16GB​	256GB​
Connection​	Multi Drop​	Multi Drop​	Point-to-Point​	Point-to-Point​
Data Resilience​	Parity​	Parity​	Parity​	CRC​

 

[DrMrLordX]

OMI is a subset of OpenCAPI? Huh! I thought OpenCAPI was going to languish and die alongside OpenPOWER.

Also if it's a serial memory interface, does that mean that installing more DDIMMs increases latency?

 

[nicalandia]

OMI is a subset of OpenCAPI? Huh! I thought OpenCAPI was going to languish and die alongside OpenPOWER.

Also if it's a serial memory interface, does that mean that installing more DDIMMs increases latency?

OMI (Open Memory Interface) Excels in Analysts’ White Paper - OpenCAPI Consortium

The Future of Low-Latency Memory – Why Near Memory Requires a New Interface April 21, 2021 17:00 ET | Source: OpenCAPI Consortium PISCATAWAY, N.J., April 21, 2021 (GLOBE NEWSWIRE) — A White Paper titled “The Future of Low-Latency Memory” by the memory and storage specialists, Objective Analysis...

opencapi.org

"OMI is a highly tuned bus derived from OpenCAPI and not only pushes the boundaries in meeting Near Memory needs, it’s an open standard and ready for adoption as products exist today. "

 

[nicalandia]

Doubtful. Remember there are many more transistors packed in together vs. Zen 3. I do think we will see 5+ ghz in many workloads, but I don’t believe it will happen with all of them (especially AVX), and unless AMD has performed some type of ritual sacrifice, I don’t think we will see single core clocks above 5.1-5.3 ghz.

Well there was Dr. Lisa Su Saying "Yes All Core at 5Ghz" While Gaming... I will take her word for it(at least for gaming)

 

[Markfw]

Well there was Dr. Lisa Su Saying "Yes All Core at 5Ghz" While Gaming... I will take her word for it(at least for gaming)

That could be. Gaming does not take 100% if 32 threads, probably not even at 16, so fewer cores could be running faster. like 2 cores maxed and 8-12 at half load ????

Edit: Those numbers are a guess, and its threads. so one physical core could be at 5.3, and 4 to 6 at 50% load or less at 5.1. Could somebody look at how many cores at what load are running in a good multi-threaded game ???

 

[Mopetar]

5 GHz all-core should be easily possible for a 7800X CPU with a 170W TDP on N5 given what's been published about it by TSMC.

I'd be surprised if a 7850X could do 5 GHz all core though. Frankly, I'm more sure it would be worthwhile for most games anyways. Dumping more of that power into getting one or two cores to boost well above that probably has better returns for gaming performance.

 

[nicalandia]

That could be. Gaming does not take 100% if 32 threads, probably not even at 16, so fewer cores could be running faster. like 2 cores maxed and 8-12 at half load ????

She did not said what type of CPU it was. Perhaps it was a 7600X or 7800X, but she said " All Cores Running at 5Ghz" its a strange statement because in gaming its better to let a few Cores reach max boost than all Cores

 

[Markfw]

She did not said what type of CPU it was. Perhaps it was a 7600X or 7800X, but she said " All Cores Running at 5Ghz" its a strange statement because in gaming its better to let a few Cores reach max boost than all Cores

Well, it seems logical to me. As you said not all cores get maxed, and so in gaming, half the CPU is not loaded or idle, so to me it makes sense that they could run at a higher speed.

 

[IntelUser2000]

They could always port the design to Intel 4. 😈

Official IFS processes are Intel 16, 3, and 18A. So they can use Intel 3.

 

[Thibsie]

Impressive and very technical sound speculation

View attachment 60423

View attachment 60424

If AMD Adopted OMI in their EPYC Architecture

If AMD Adopted OMI in their EPYC Architecture - Download as a PDF or view online for free

www.slideshare.net

Charlie had an article about new stuff in Genoa. Might be CXL.mem.

 

[eek2121]

Well there was Dr. Lisa Su Saying "Yes All Core at 5Ghz" While Gaming... I will take her word for it(at least for gaming)

As I recall, the claim wasn't even about gaming in general, but rather, Halo. For reference, my 5950X gets somewhere around 4.6-4.7 GHz (can't remember the exact numbers), whereas other workloads, or even more demanding games, may drop that number lower. Prime95 will even bring my 5950x down below the base clock (unless I enable PBO).

Also, frequency is very deceptive. See: Effective clock vs instant (discrete) clock

 

[A///]

AMD is cooking up something special for DDR5. It is very likely Zen 4 is going to be the best gaming chip out there.

Let's not get ahead of ourselves here. AMD has improved for the better and outpaced Intel in some areas, but this reads like typical AMD marketing tripe.

 

[A///]

That could be. Gaming does not take 100% if 32 threads, probably not even at 16, so fewer cores could be running faster. like 2 cores maxed and 8-12 at half load ????

Edit: Those numbers are a guess, and its threads. so one physical core could be at 5.3, and 4 to 6 at 50% load or less at 5.1. Could somebody look at how many cores at what load are running in a good multi-threaded game ???

When I first heard it I was still dealing with holiday indulgent, I took it as literally as one could. 5 ghz on all cores. She didn't state what kind of processor it was and later material from AMD didn't say anything either.

I could see it working on a six core design but the r9 layouts? That's just crazy if they can hit and maintain those speeds. Either their words are open to interpretation or she said it wrong and meant boost on multiple cores.

 

[biostud]

There's hardly any reason to boost all cores if they aren't doing any work? And how many games put a load on all cores.

The 5 Ghz all core statement only makes sense if the CPU is under full load, otherwise I would prefer my cores not to boost and save energy. Or is there something I'm missing?

 

[igor_kavinski]

AMD has improved for the better and outpaced Intel in some areas, but this reads like typical AMD marketing tripe.

Yeah, agree totally. They marketed 5800X3D like it was the undisputed gaming king in ALL games. It's not. That was a bit of a letdown. Maybe their marketing department has some ex-Intel employees now.

 

[A///]

Yeah, agree totally. They marketed 5800X3D like it was the undisputed gaming king in ALL games. It's not. That was a bit of a letdown. Maybe their marketing department has some ex-Intel employees now.

It's a good sku, but it doesn't make sense unless you're already using 5600x or older processor from the 3, 2 or 1 line with a compliant mobo. Right now you can buy into Zen 3 with a cheap 5900X and it'll be good for a few years barring any major leaps from either Intel or AMD. If you need to upgrade now, I'd hold off until they both drop their goods and see which one is better for consumers.

 

[A///]

Double post, apologies.

 

[ZGR]

Let's hope by the time Ryzen 6000 is rolling out, DDR5 prices are more palatable. It was frustrating for Broadwell-E and early Skylake owners to buy rather slow DDR4 and then want to upgrade again. But with how DDR5 6000+ performs, that probably won't be as big of a concern. I hope AMD is going to have nice high speed DDR5 support right out of the gate.

 

[biostud]

While DDR5 is 6000+ is double the cost of DDR4 4000+, it is a relatively small fraction of the total cost of a completely new computer, if you have to do a full upgrade.