Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Shivansps]

Mmm then this is why there is 4 extra pcie lanes "for a 2nd m2".

 

[poke01]

7950X on MT Cinebench is hitting 38,000

That is a rumour that was told by a AMD-centric YT channel. take it with a grain of salt

 

[Henry swagger]

That is a rumour that was told by a AMD-centric YT channel. take it with a grain of salt

His bias can't even hide it.. even deleted his old zen 4 leak videos lol

 

[poke01]

His bias can't even hide it.. even deleted his old zen 4 leak videos lol

lol. 15%-20% IPC and up to 37% ST right?

What a bunch of lies

 

[Hitman928]

I've said it before as have others, MLID and these other 'leakers' are not reliable sources. Of course, next gen we'll start the cycle again and people will be posting their stuff like it is legitimate and maybe they'll get lucky and guess a few things right, but discussing these rumors without a huge amount of pessimism is just a waste of time, IMO.

 

[Exist50]

Yeah, this caught a lot of people off guard, including people like Andrei who write about such things for a living. I distinctly remember Andrei saying multiple times before the details of the Golden Cove architecture became known that increasing the decoders beyond 4 would be very problematic in x86 architectures due to the variable length of the instructions. This sort of commentary would usually be used when comparing Apple CPUs to x86.

But Intel did just that and smashed through that barrier, and Golden Cove is obviously very performant. Doubling the fetch bandwidth to 32 bytes was also another big deal so I was told.

It will be interesting to see whether AMD stays with 4 decoders in Zen 5. Eventually they will have to go wider to keep up with Intel I believe, because Golden Cove will be used as a foundation for the advancements of future Intel CPUs.

Yeah, 4-wide was never an inherent limitation of x86. I think AMD will almost certainly go 6-wide with Zen 5, assuming they're on the same ~1.5 year cadence as they have been. Would even expect that Intel will go 8-wide in a similar timeframe (circa Lion Cove?), so Zen 5 will surely have to be at least 6-wide to keep up. Though that said, I think Zen 4 is doing very well with a more restrained approach than Intel. I'd even say it's a better overall core considering the server market.

Zen 5 will be interesting, indeed. AMD Corporate Fellow and "Zen" lead Mike Clark is apparently giddy about it, and as I recall, CPU guru Jim Keller in interviews has been pretty optimistic about opportunities for more IPC gains through more decode bandwidth and larger instruction windows for out-of-order execution. No end in sight.

I don't see any fundamental roadblocks to further scaling. Even ignoring Royal, I could easily see 10-wide architectures 5 years from now. I'm curious how AMD's going to approach it for example. Monolithic like Core, clustered like Atom, or something of their own?

Though all that said, I don't think Zen 4 is just a shrunk Zen 3 with other bits and bobs tacked on. Expect more details to come out eventually, but it's a pity AMD doesn't seem to be talking about it at Hot Chips.

 

[Timorous]

lol. 15%-20% IPC and up to 37% ST right?

What a bunch of lies

Or you can look at the blender result.

AMD said it was 31% faster but from the 204s and 297s for Zen 4 and 12900K respectively their figure is wrong.

Zen 4 is actually 45% faster than the 12900K in this test. As it is a short blender run the 12900K is about the same or a bit faster than the 5950X but even a 40% uplift in CB R23 MT would put a 16c Zen 4 part at around 40,000 points.

It is of course possible that Blender likes Zen 4 more than CB does but 38,000 points is not out of the question when you take a close look at the blender data.

 

[poke01]

Or you can look at the blender result.

AMD said it was 31% faster but from the 204s and 297s for Zen 4 and 12900K respectively their figure is wrong.

Zen 4 is actually 45% faster than the 12900K in this test. As it is a short blender run the 12900K is about the same or a bit faster than the 5950X but even a 40% uplift in CB R23 MT would put a 16c Zen 4 part at around 40,000 points.

It is of course possible that Blender likes Zen 4 more than CB does but 38,000 points is not out of the question when you take a close look at the blender data.

I am talking about ST. Blender is MT

 

[itsmydamnation]

I am talking about ST. Blender is MT

Yeah but who wants to buy a crappy backwards CPU that doesn't even support AVX-512

/intel fans Circa rocket lake
/probably

Also i wouldn't go counting your IPC chickens before they hatch, otherwise you might get the sads and that would be sad

 

[deasd]

lol. 15%-20% IPC and up to 37% ST right?

What a bunch of lies

at least the 8-14% frequency uplift claim seems 100% fit into LisaSu's presentation, ~5.52Ghz is ~14% higher than 5950x.

IPC is an ambiguous claim I never take that too seriously, if you see the Zen3vsZen2 perf summary that was released by AMD in 2020 you can see the R15 is boosted up to ~18% IPC while other items are far from 18%, and AMD claimed Zen3 is ~19% IPC uplift. If you take official '>15% ST' seriously then you fall into another trap whatever you trying to deprecate or hype.

Yeah but who wants to buy a crappy backwards CPU that doesn't even support AVX-512

what's worth mentioning is AVX512 is one of the biggest change for Zen4, since AVX512 could vastly increase 'IPC' in some situation but Lisa didnt even try to hype it. especially when AVX512 was disabled in desktop GoldenCove.

 

[jamescox]

So anyone has any idea of why two chipsets?

Pci-express 5 has significantly lower trace length limitations due to signal integrity at the ridiculously high clock speeds. Using two chips allows pci-express 5 speeds for all components while keeping the trace lengths short. The chip used is possibly the same as an IO die used on the cpu or very similar.

 

[IntelUser2000]

I've said it before as have others, MLID and these other 'leakers' are not reliable sources.

I don't know why there's so much flak, especially with MLID. XeSS, Redwood Cove, Alderlake and Raptorlake, they were all leaked by him. Adored, I think it's just for fun and the RedGamingTech or whatever is mostly BS.

As people have said before he's been pretty much spot on with Intel leaks. I don't think getting it wrong once disqualifies him entirely. I can't say too much about AMD and Nvidia but I wouldn't ignore him entirely either.

Kinda similar mentality to firing a 20 year employee that failed on his promoted position. One failure disqualifies you for hundreds of successes over 20-plus years? Just demote him and put him elsewhere.

 

[jamescox]

Speaking of which, do we have any idea how big the Bergamo chiplet is?

I thought the idea was that it is similar in size to the regular 8 core chiplet since it uses a denser process and may have less cache or a different cache organization. I was thinking that it may use stacking in some manner. For a low power, high end device, it would make sense to use silicon bridges rather than high clocked serdes. If it does use stacking, then it would probably be incompatible with the desktop IO die. I have to wonder if Zen 4+ will use some stacking though.

 

[jamescox]

Looks like a workstation platform to me with 8 DIMM slots, probably quad channel.

It is still AM5 with only 2 channels (technically 4x32 channel rather than 2x64). The two chips are just to get pci-express 5 speeds to all components on the board. Pci-express 5 speeds require shorter trace lengths to maintain signal integrity.

 

[jamescox]

No, not with the package as currently designed. I'm guessing the IOD would have to grow as well to support more chiplets.

The IFOP interfaces are not that large. The original Zen 1 Zeppelin die has 4 IFOP with only 3 of them used. It was just to reduce routing complexity in the Epyc package. I don’t think adding the IFOP would be much of a limitation. It doesn’t look like we are going to get more than 2 chiplets with the initial Zen 4. We might get a stacked version for Zen 4+, so that could open up some possibilities. The only other thing I can think of is if they added two IFOP links to an APU die, but that is probably incredibly unlikely, even if it makes some sense.

 

[IntelUser2000]

Agree. They have to balance between energy saving margin and speed margins.
So based on these revelations and after back calculation I can say with certainty the demo ran without OC and very much at stock limit. The IPC at the low end seems to be 3%. There might be room for up to 20% power for OC, tweak and distribute... but I'm not too certain due to diminishing return.

Don't know about whether they needed to balance things, but the other guy saying AM5 requiring a big platform change for the first time in many years makes sense to me. They were on AM4 for years.

We'll see what these numbers really mean. Is it 45% gain over Alderlake in Blender and Zen 3, or was Zen 3 already 10-20% faster than Alderlake in that particular benchmark? Maybe some of the gains are AVX512?

 

[jamescox]

I dont think that he meant all-core turbo to be 5,2 to 5,5 during gaming. Just that iregardless of what core or core or cores are assigned to the game, all are capable to boost that high.

On topic of Adored TV - as he shows Lisa Su holding that prototype CPU in hand on Computex, he speculates those chiplets could actually hold more cores than 8 or that they might be space for another chiplet(s) - to support his former claim there will be more cores. Too bad at that particular time and place she says in the video literally "as you can see, Ryzen 7000 include up to 2 core chiplets, each with 8 Zen4 cores...." I presume this is why some people refuse to watch his stuff.

The quote posted above says 5.2 to 5.5 for all threads playing that game, so that sounds like over 5 GHz all core, if that quote is correct.

 

[Exist50]

As people have said before he's been pretty much spot on with Intel leaks. I don't think getting it wrong once disqualifies him entirely. I can't say too much about AMD and Nvidia but I wouldn't ignore him entirely either.

Even if you ignore a pretty poor track record with any company but Intel (which frankly is plenty enough reason to criticize), he's gotten a number of things wrong with Intel too, including "current" information. He clearly has some info source, but it's mixed with so much BS that he's not terribly useful. I know we're still waiting for proper Zen 4 numbers, and I'm even optimistic, but quite clearly the early claims of >30% single thread from various leakers were way off base.

 

[lobz]

Sorry, I meant cleaning the paste out of the notches.

now THAT is going to be a headache for sure

 

[IntelUser2000]

I know we're still waiting for proper Zen 4 numbers, and I'm even optimistic, but quite clearly the early claims of >30% single thread from various leakers were way off base.

Clearly it's a fight between desire for companies to keep the information about future products secret and controlled versus outsiders wanting to know and discuss about it.

You had reliable leakers like Ashraf Eassa being hired away by Intel.

It is an exercise in futility if you get too serious about it. Either you are under NDA and can't reveal it, or is an outsider and will miss. I think they eventually find out who's leaking the info and start making that very guy shut up or leak wrong information to throw everyone off.

 

[coercitiv]

I can't say too much about AMD and Nvidia but I wouldn't ignore him entirely either.

I'll say this once more time: the man deletes videos when his analyses & predictions go haywire. His track record is therefore manufactured.

A couple of links gathered 2 years ago by a reddit user:

• Zen 4 vs Golden Cove, a video full of fan fiction tier analysis = nuked off the earth
• "Zen 4 will have SMT4, 100% sure" = nuked
• Video about a Navi lineup that was completely false = nuked
• Another Navi lineup "leak"? = nuked
• Threadripper fanfiction? = nuked
• Zen 3 I/O die speculation = nuked

 

[lobz]

I don't know why there's so much flak, especially with MLID. XeSS, Redwood Cove, Alderlake and Raptorlake, they were all leaked by him. Adored, I think it's just for fun and the RedGamingTech or whatever is mostly BS.

As people have said before he's been pretty much spot on with Intel leaks. I don't think getting it wrong once disqualifies him entirely. I can't say too much about AMD and Nvidia but I wouldn't ignore him entirely either.

Kinda similar mentality to firing a 20 year employee that failed on his promoted position. One failure disqualifies you for hundreds of successes over 20-plus years? Just demote him and put him elsewhere.

Also, let's just wait and see before we can say if this was a failure. I don't think we can say that almost half a year before release. Anyone who thinks that Zen4 will operate at 14% higher ST clock for '>15%' performance gain is out of their mind.

 

[Exist50]

Also, let's just wait and see before we can say if this was a failure. I don't think we can say that almost half a year before release. Anyone who thinks that Zen4 will operate at 14% higher ST clock for '>15%' performance gain is out of their mind.

If Zen 4 was 37% faster in ST, they would have given a number better than 15%. There's some wiggle room, sure, but I think hoping for more than twice the given number is extremely unrealistic.

 

[uzzi38]

I don't know why there's so much flak, especially with MLID. XeSS, Redwood Cove, Alderlake and Raptorlake, they were all leaked by him. Adored, I think it's just for fun and the RedGamingTech or whatever is mostly BS.

As people have said before he's been pretty much spot on with Intel leaks. I don't think getting it wrong once disqualifies him entirely. I can't say too much about AMD and Nvidia but I wouldn't ignore him entirely either.

Kinda similar mentality to firing a 20 year employee that failed on his promoted position. One failure disqualifies you for hundreds of successes over 20-plus years? Just demote him and put him elsewhere.

Rule MLID out for anything AMD and Nvidia. He is wrong a LOT more often then he is right.

 

[deasd]

Some eagleeye found that two core dies are tighter than before:

https://twitter.com/x/status/1529297282125791233