Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[igor_kavinski]

Yay! More traffic for AT forums.

 

[RTX2080]

Your post got picked up by VIdeocards . They are lurking these forums after all.

AMD Ryzen 7 7700X Zen4 CPU pictured up close - VideoCardz.com

AMD Ryzen 7 7700X Raphael CPU pictured Over at AnandTech forums there is a picture of the upcoming Ryzen 7 7700X CPU. The photo shows how the final version of AMD Raphael 8-core CPU is going to look like. This is the first time we are seeing laser engraving with proper AMD Logo and SKU […]

videocardz.com

Oh nooo lol... I'm not a source. It is from a random person which is likely not bounded by NDA. He just left this photo without any message. So that's why I describe it as "Unknown source". I'm not sure whether the photo has already been posted somewhere else before.

回复：锐龙7000来了，国外都上架了【amd吧】_百度贴吧

锐龙7000来了，国..回复 YY都是自己人 :我从1400用到5600x 以后不会碰amd 任何产品，狂潮的时候，6800卖的比3080都贵，你把amd当信仰amd 把你当

tieba-baidu-com.translate.goog

As you can see the image is upside down originally so I decide not to rolate it.

Hope he tells us how does it feel to be famous now

I feel sick. It's misunderstanding. I edit my post. Very sorry.

 

[inf64]

Oh nooo lol... I'm not a source. It is from a random person which is likely not bounded by NDA. He just left this photo without any message. So that's why I describe it as "Unknown source".

回复：锐龙7000来了，国外都上架了【amd吧】_百度贴吧

锐龙7000来了，国..回复 YY都是自己人 :我从1400用到5600x 以后不会碰amd 任何产品，狂潮的时候，6800卖的比3080都贵，你把amd当信仰amd 把你当

tieba-baidu-com.translate.goog

As you can see the image is upside down originally so I decide not to rolate it.



I feel sick. It's misunderstanding. I edit my post. Very sorry.

All is good man, no need to edit the post. You sent a very nice piece of information, I figured it's from one of the forums you lurk

 

[Timmah!]

I feel sick. It's misunderstanding. I edit my post. Very sorry.

Oh no need to be sorry or feeling sick (if meant serious), i was just trying to be funny
Could not care less about the source of the picture otherwise.

 

[igor_kavinski]

@cortexa99 Destiny has chosen you. Better start working on your new found purpose

 

[Exist50]

While IIRC it was stated by an AMD rep that bergamo was cloud specific (no desktop), it would not surprise me at all if AMD pushes out a desktop version down the road. Note that 3D V-Cache would negate the hit by halving L3. AMD could do a 32c/64t Ryzen chip pretty easily with just two chiplets.

There's very little overlap between desktop workloads that would benefit from a lot of cache, but wouldn't be harmed by a significant hit to peak frequency. I really don't think such a product would make sense.

 

[RTX2080]

https://twitter.com/x/status/1559897403532394501

ROB 320，OP Cache 6.75K

for comparison:
zen2: 224 rob, 4k op cache
zen3: 256 rob, 4k op cache

edit: wow the twitter link got killed quickly!

Oh no need to be sorry or feeling sick (if meant serious), i was just trying to be funny
Could not care less about the source of the picture otherwise.

@cortexa99 Destiny has chosen you. Better start working on your new found purpose

My bad. I'm just a lurker. I hope Lisa Su doesn't call FBI to break my house's door just for searching Zen4 CPU cuz it's not the right place.

 

[igor_kavinski]

I hope Lisa Su doesn't call FBI to break my house's door just for searching Zen4 CPU cuz it's not the right place.

Nah. If they wanna find someone, they will find the person who was given that exact CPU by AMD. Not the person who currently has it.

 

[inf64]

https://twitter.com/x/status/1559897403532394501

ROB 320，OP Cache 6.75K

for comparison:
zen2: 224 rob, 4k op cache
zen3: 256 rob, 4k op cache

edit: wow the twitter link got killed quickly!






My bad. I'm just a lurker. I hope Lisa Su doesn't call FBI to break my house's door just for searching Zen4 CPU cuz it's not the right place.

I think that you don't need to worry about FBI or AMD, if they want to find out who leaked it, they can easily do that. I suspect that the CPU in question was obtained via regular retail sales channel.

Regarding the ROB and uOP cache, do you know who (username) posted this on twitter? The differences in ROB and uOP cache sizes are pretty significant, much larger than Zen 2 ->Zen 3

 

[Timmah!]

My bad. I'm just a lurker. I hope Lisa Su doesn't call FBI to break my house's door just for searching Zen4 CPU cuz it's not the right place.

So you keep it elsewhere, i presume some secret hideout of yours. Very smart!

 

[Tuna-Fish]

ROB 320，OP Cache 6.75K

edit: wow the twitter link got killed quickly!

Regarding the ROB and uOP cache, do you know who (username) posted this on twitter? The differences in ROB and uOP cache sizes are pretty significant, much larger than Zen 2 ->Zen 3

Yeah, I'm also very curious. That ROB change would prove me wrong, I expected minimal changes inside the core itself, just cache/system level stuff (+AVX512).

 

[inf64]

Yeah, I'm also very curious. That ROB change would prove me wrong, I expected minimal changes inside the core itself, just cache/system level stuff (+AVX512).

Well it makes sense in light of Angstronomics' leak:

"As for the claimed Single-Thread Uplift of ‘greater than 15% expected‘, Angstronomics can confirm this is a conservative value, done at below final frequencies and using Maxon’s Cinebench R23 Single Thread Benchmark. We can independently confirm that the Performance Per Clock (PPC) targets for the Zen4 core are targeted at +7% Single-Thread PPC, +10% Multi-Thread PPC over their Zen3 core, with significantly higher PPC for memory sensitive workloads thanks to DDR5 while core execution bound workloads like Cinema4D have a lower PPC improvement. "

Significant uplifts in memory sensitive workloads (>20%) can be expected with changes like the tweet above suggests.

 

[igor_kavinski]

So you keep it elsewhere, i presume some secret hideout of yours. Very smart!

Hey! Don't scare him

 

[RTX2080]

I think that you don't need to worry about FBI or AMD, if they want to find out who leaked it, they can easily do that. I suspect that the CPU in question was obtained via regular retail sales channel.

I'm just joking. Earlier post was from china. AMD would know it immediately if they read the post I edited.

Regarding the ROB and uOP cache, do you know who (username) posted this on twitter? The differences in ROB and uOP cache sizes are pretty significant, much larger than Zen 2 ->Zen 3

https://twitter.com/xinoassassin1

He sounded like not wanna being known but he still made leaks and deleted. Very funny.

I don't know how much ROB/uOPcache affect performance but Iooks like the front end is very wide...? (although the decode depth is unknown)

 

[nicalandia]

I can believe halving the L3 for Bergamo. Maths on that just works really. Die size is around 75-80 and with Zen 3 32MB of L3 took up about half of that area. With N5 offering better logic scaling than cache scaling it stands to reason 32MB of L3 will be around 2/3s of the die area give or take leaving 1/3 for cores. Well if you half that L3 you end up with 1/3 cores and 1/3 cache allowing you to add another 8 core cluster for a 16c CCD and use a very similar amount of die area.

Thats been my take al along.

 

[Timmah!]

View attachment 66046

OK, lets talk the IHS design, i mean the text printed on top. I dont like it at all. I mean, the logo is fine, though could be smaller, or even better AMD logo would suffice. The name of the CPU, thats given, Ryzen 7 7700x indeed, but whats up with the rest, bunch of codes and the QR code, why?
Give me number of cores, base clockspeed and say size of cache (L3 + L3) instead that crap, something like 6C/4,4GHz/40MB.

 

[Saylick]

OK, lets talk the IHS design, i mean the text printed on top. I dont like it at all. I mean, the logo is fine, though could be smaller, or even better AMD logo would suffice. The name of the CPU, thats given, Ryzen 7 7700x indeed, but whats up with the rest, bunch of codes and the QR code, why?
Give me number of cores, base clockspeed and say size of cache (L3 + L3) instead that crap, something like 6C/4,4GHz/40MB.

Because they assume you can read the brochure and don't need it on the actual product, which gets covered up anyways with the cooler. You don't see car manufacturers labeling the car's horsepower, curb weight, and 0-60 times on it's exterior, right?

 

[coercitiv]

The name of the CPU, thats given, Ryzen 7 7700x indeed, but whats up with the rest, bunch of codes and the QR code, why?
Give me number of cores, base clockspeed and say size of cache (L3 + L3) instead that crap, something like 6C/4,4GHz/40MB.

Rather than architectural info that you can easily find online, it makes much more sense to include manufacturing and commercial info such as:

• Ordering Part Number: 100-000000591
• Batch: BQ 2226PGY (encodes year/week of production, also the assembly site and the diffusion site)
• Serial Number: 9KN1101T20077 (in case you want some warranty instead of a base clock tattoo)

And finally, the QR code contains the Serial Number and OPN in a single string (9KN1101T20077_100-000000591), probably a useful thing for fast processing inside various facilities.

Personally I'm thankful you're not in charge of IHS design for any company.

 

[inf64]

Skyjuice60 posted on twitter that the 7700X pictured is not a retail sample:

https://twitter.com/x/status/1559886356809011200

 

[coercitiv]

Skyjuice60 posted on twitter that the 7700X pictured is not a retail sample:

I was wondering what that "D" stood for, now we know.

 

[Timmah!]

Because they assume you can read the brochure and don't need it on the actual product, which gets covered up anyways with the cooler. You don't see car manufacturers labeling the car's horsepower, curb weight, and 0-60 times on it's exterior, right?

Nor do you see its Ordering Part Number or Batch Number nowhere on the car, so not sure why do you think car analogy is good one.

 

[Saylick]

Nor do you see its Ordering Part Number or Batch Number nowhere on the car, so not sure why do you think car analogy is good one.

I mean, the analogy for the car is the trim, VIN number, and production date, which is shown on the sticker in the driver's side door.

 

[Timmah!]

Rather than architectural info that you can easily find online, it makes much more sense to include manufacturing and commercial info such as:

• Ordering Part Number: 100-000000591
• Batch: BQ 2226PGY (encodes year/week of production, also the assembly site and the diffusion site)
• Serial Number: 9KN1101T20077 (in case you want some warranty instead of a base clock tattoo)

And finally, the QR code contains the Serial Number and OPN in a single string (9KN1101T20077_100-000000591), probably a useful thing for fast processing inside various facilities.

Personally I'm thankful you're not in charge of IHS design for any company.

I am sure you frequently use all that info printed on the CPU. Especially when you have cooler mounted on top of it

 

[arcsign]

W.r.t. ROB and op cache changes, if you’re unsure why those are interesting (like I was about 10 min ago), chips and cheese analysis of zen3 bottlenecks is pretty helpful.

(unrelated, holy cow, I created this account 13 years ago and apparently just never used it?)

 

[Saylick]

W.r.t. ROB and op cache changes, if you’re unsure why those are interesting (like I was about 10 min ago), chips and cheese analysis of zen3 bottlenecks is pretty helpful.

Holy lurker camoley.

Relevant quotes:

The Reorder Buffer (ROB) is the part of the core that allows ops to be executed out of order relative, by tracking the instructions in the original program order. The ROB being full is the most common reason for the core to stall, and is responsible for stalling the renamer about 8 to 20% of the time. In a way, that’s a good thing, because it means the core’s not stalling on other structures first. AMD has done a good job with profiling workloads and sizing Zen 3’s various OOO queues, so Zen 3 is quite often running into the limit of how many instructions it can keep in-flight.

As we can see from the chart, War Thunder at 7.343% of the time missing the Op Cache has the highest miss rate of all the applications with 3DMark Timespy and EU4 at 2nd and 3rd place respectfully.

This suggests these 3 applications use the decoders quite often because the amount of instructions that are being streamed doesn’t fit into the 4K entry Op Cache that Zen 3 has where as Linpack’s instruction stream fits into the Op Cache.