Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[DisEnchantment]

That looks nice! What's the CLI tool you used to print these? Thanks.

I am using this

GitHub - hattedsquirrel/ryzen_monitor: Monitor power information of Ryzen processors via the PM table of the SMU

Monitor power information of Ryzen processors via the PM table of the SMU - hattedsquirrel/ryzen_monitor

github.com

But I am going to write a new Application with QML to read the data from the SMU kernel driver and have a proper GUI like on Windows with HWInfo (If I don't find one by the time Zen4 launches)
I have actually written one service which reads the data and send to GRPC to my RPi with a display attached to my transparent side panel, I have one app on my Smartphone also showing the Stats on Android App via WiFi and now I will write one for natively showing on the Linux Desktop.
Seems I got too much time on my hands.

 

[Exist50]

I'm kinda disappointed nobody seems to have really thought about what AMD talked about with regards to Zen 4C honestly.

Same ISA support, same IPC, and now also confirmed to use half of the core area (key word being core, mind you).

That puts Zen 4C in similar size regions to ARM cores such as V1. That's kind of a big deal.

And beyond just the raw performance/efficiency improvements, it does all that in a package that is (presumably) hardware, firmware, and software compatible with Genoa. That is a huge selling point to CSPs.

 

[Carfax83]

So 6000mhz for DDR5 right out the box maxes out the 1:1 fabric clock on Zen 4?

That's what the leaks implies, in addition to the AMD presentation. 3ghz is a big jump from Zen 3 though to be sure.

DDR5 is only barely a year old. Does that mean DDR6 is right around the corner?

What makes you say that? This is just how Zen's chiplet based memory architecture works. Zen 3 was similar. Remember this slide?

Higher ratios will be available to be sure so you will be able to run higher frequencies that DDR5 6000, but the latency will probably be higher than running at a lower speed in 1:1.

 

[uzzi38]

I guess I missed it. Did Papermaster talk about that? Or is it somewhere else? Press mentions of Zen 4c seem to be limited to it using N4.

Not sure where it was in the presentation, because I didn't watch the full thing, was suffering from a pretty bad flu at the time.

 

[Rigg]

Please do you know the settings that Ram run in the ADL system? Do you know if it ran at CL30? What about the other timings?

Presumably both test systems ran the same timings. I'm not a lawyer, but I assume using highly misleading test variables in a public presentation could have serious legal consequences. While none of us can say for sure what the exact memory settings for either system were I think it's safe to assume they were the same for both.

It's not far fetched for any enthusiast worth their salt to understand that putting an AMD EXPO tuned RAM into a non EXPO rated bios, much more a non AMD system, isn't going to run optimally. This is not so hard to understand. The 7600x run optimally. The ADL didn't. Add the cherry-picked games on top and you should understand why your "winning in games" comment is not only laughable but smacks of gullibility since these are not even third-party reviews but AMD slides. If nothing at all, history should teach us to exercise some patience until we get reviews from other sources since this isn't the first time AMD has pulled this sort of stunt with their gaming numbers.

This is pure assumption. Any 1 click mem oc is likely to be non optimal on either platform. Have you seen the crap sub-timings on an XMP profile? Memory kit vendors sell kits based on speed and primary timings. They use crap subs for stability. AMD's own version of XMP isn't going to magically change that.

Even if the Intel test setup isn't 100% optimal, it's EXTREMELY unlikely to show any significant performance difference in anything but memory specific synthetic benchmarks or 720p game benches. This isn't hard for an enthusiast worth their salt like you to understand though. Amirite?

You're delusional if you think that a few sub timings POSSIBLY being less than optimal has handicapped the 12900k in any significant way. Clinging to this kind of minutiae is kind of hilarious. I'd find it entertaining but now it's just getting annoying.

 

[coercitiv]

I guess I missed it. Did Papermaster talk about that? Or is it somewhere else? Press mentions of Zen 4c seem to be limited to it using N4.

Not sure where it was in the presentation, because I didn't watch the full thing, was suffering from a pretty bad flu at the time.

It's briefly mentioned in the presentation, except he did not make the claim for same IPC.

 

[igor_kavinski]

AMD Ryzen 7950X3D, 7900X3D and 7800X3D tipped for CES 2023 launch - VideoCardz.com

If they try just a little bit harder, they could release these by end of December.

 

[uzzi38]

It's briefly mentioned in the presentation, except he did not make the claim for same IPC.

The IPC bit is from previous times they've talked about Zen 4C, although I should point out that the claim is made when discussing cloud workloads specifically, no clue how it would hold up for general serever/HPC or even client loads.

 

[Exist50]

The IPC bit is from previous times they've talked about Zen 4C, although I should point out that the claim is made when discussing cloud workloads specifically, no clue how it would hold up for general serever/HPC or even client loads.

At most, they'd lose a tiny bit of IPC due to cache differences. In terms of the rest of the core, should be 100% identical.

 

[PJVol]

It will be just like Zen 3 in the sense that 1:1 ratio will be the best for performance. Running the memory at higher speeds than the FCLK will increase bandwidth but probably result in a latency penalty

Sorry, I can't see what bios nvar caps that Yuriy got from the am5 fw has to do with the max achievable frequency, namely FCLK. All recent AM4 uefi fw such as that for my B550 board allows FCLK to be set up to 3000Mhz as well, but for the 5600X max is ~ 2100-2133.
As follows from EXPO info, there are low latency (sync) and high bandwidth (async) modes, so the actual DDR5 speed in amd lab tests tells nothing about which one was used.

I am using this

The program layout looks broken for me in KDE terminal. I've reported an issue long ago but the author seem to abandon the project.

 

[ondma]

Man, you're definition of grasping a straw.
If anand will continue their policy in test you won't see Alder Lake tested with 6000 DDR5. They test (and rightfully) with rated speed by chip producer, so 4800 for Alder Lake and 5200 for Zen 4 (and with 5600 for RL). It will be even worse for AL. The same will be in many other reviews, because that's DDR5 RAM speed both producers guarantee at stock.
Overclocking RAM is pita (especially testing) and not many people do it. They wanna know what performance is when they put their kit in mainboard go to BIOS set profile and that's all. That's why reviews (and again rightfully) don't optimize usually any RAM settings.

And latency is not good indicator of anything. It's only for the first block of data from memory, and you have to transfer many many blocks at one time. That's one of the reasons why Rocket Lake was no match for Zen 3 in games, despite having 10 ns better latency than Zen 3.

Yea, maybe Anand will even continue to test with their 2080 dgpu. Honestly, I have given up on getting anything useful from Anand gaming tests a long time ago. As for sticking to rated memory speeds, it just seems unrealistic that someone is going to buy a top of the line cpu and motherboard and not overclock the memory.

 

[Kaluan]

If we ignore all that high frequency copper melting inferno happening now and compare the single core output at nice cool enviromentally friendly 3600 MHz, we get this:

View attachment 66900

If I remember correctly, AMD stated that the new CPUs are 9% better at Cinebench than 5000 series CPUs. That would mean 508 points for Zen 4 - that is still slower than Alder lake.

Oh nooo, what will they ever do?!? 1-threaded Cinema4D rendering farms will be absolutely dominated by Intel CPUs!!! lol

Here is the King.
View attachment 66903

GIGABYTE W771-Z00-00 - Geekbench

Benchmark results for a GIGABYTE W771-Z00-00 with an AMD Ryzen Threadripper PRO 5995WX processor.

browser.geekbench.com

I mean King of Release and September Release CPUs. Because this guy Zen4 Genoa is just bullying anything that comes near GB...

View attachment 66905

Can someone tell me why do we think that's Genoa and not Bergamo? Mostly because I don't understand why does the L3 show up as 12x16MB and not 32MB.

Also up to how many threads can GB 5.2 scale to? I know CB R20/R23 scale to just 256, which make benching dual-socket Genoa and Bergamo semi-useless.

 

[nicalandia]

Can someone tell me why do we think that's Genoa and not Bergamo? Mostly because I don't understand why does the L3 show up as 12x16MB and not 32MB.

It's likely a reading error of GB.

For example Zen4 ES Sample is listed as 16x4 By Geekbench, but on Sisoftsandra the L3 is read successfully.

AMD Eng Sample: 100-000000897-03

Suma R6250A0 - Geekbench

Benchmark results for a Suma R6250A0 with an AMD Eng Sample: 100-000000897-03 processor.

browser.geekbench.com

Details for Result ID 2x AMD Eng Sample: 100-000000897-03 (4M 32C 64T 3.5GHz, 1.6GHz IMC, 32x 1MB L2, 4x 32MB L3)

Details for Result ID 2x AMD Eng Sample: 100-000000897-03 (4M 32C 64T 3.5GHz, 1.6GHz IMC, 32x 1MB L2, 4x 32MB L3)

ranker.sisoftware.co.uk

 

[Kaluan]

It's likely a reading error of GB.

For example Zen4 ES Sample is listed as 16x4 By Geekbench, but on Sisoftsandra the L3 is read successfully.

AMD Eng Sample: 100-000000897-03

Suma R6250A0 - Geekbench

Benchmark results for a Suma R6250A0 with an AMD Eng Sample: 100-000000897-03 processor.

browser.geekbench.com

Details for Result ID 2x AMD Eng Sample: 100-000000897-03 (4M 32C 64T 3.5GHz, 1.6GHz IMC, 32x 1MB L2, 4x 32MB L3)

Details for Result ID 2x AMD Eng Sample: 100-000000897-03 (4M 32C 64T 3.5GHz, 1.6GHz IMC, 32x 1MB L2, 4x 32MB L3)

ranker.sisoftware.co.uk

Ah great, got it. Thank you!

 

[eek2121]

REALLY unsure why people keep bringing up memory speed/timings when for most workloads you are looking at a 1-3% difference, which is basically margin of error.

 

[leoneazzurro]

That's what the leaks implies, in addition to the AMD presentation. 3ghz is a big jump from Zen 3 though to be sure.



What makes you say that? This is just how Zen's chiplet based memory architecture works. Zen 3 was similar. Remember this slide?

Higher ratios will be available to be sure so you will be able to run higher frequencies that DDR5 6000, but the latency will probably be higher than running at a lower speed in 1:1.

Well it seems your leaks were wrong

https://twitter.com/x/status/1565012130746998784

 

[leoneazzurro]

The IPC bit is from previous times they've talked about Zen 4C, although I should point out that the claim is made when discussing cloud workloads specifically, no clue how it would hold up for general serever/HPC or even client loads.

If the main difference is cache size (and secret sauce of course) on can see that ipc may be the same for the workloads Bergamo is targetted for. And more than probably max clocks will be lower as well.

 

[exquisitechar]

REALLY unsure why people keep bringing up memory speed/timings when for most workloads you are looking at a 1-3% difference, which is basically margin of error.

For gaming, there are massive differences.

Well it seems your leaks were wrong

https://twitter.com/x/status/1565012130746998784

Yeah, Raichu was right. Disappointing, but not unexpected.

 

[nicalandia]

Disappointing, but not unexpected.

Jesus Christ. Disappointing and Ryzen 7000 should be mutually exclusive. I mean Come On..!

 

[Zucker2k]

Well it seems your leaks were wrong

https://twitter.com/x/status/1565012130746998784

Well, the default fclk is 1733, and doesn't run 1:1 with uclk and mclk. So, what you have is:
1733 : 2600 : 2600.
AMD ran:
2000 : 3000 :3000.
FCLK : UCLK : MCLK

 

[CakeMonster]

If I understand him correctly there doesn't seem to be any required ratio between the former and the two latter at least (for optimal performance).

 

[Kaluan]

For gaming, there are massive differences.

They obviously meant the 6000CL30 v 6400CL32 that that Shady guy (and a few others) keeps bringing up.

Also nope either way. 10% better avg and say, 15% better percentile in extreme stock vs ultra-tuned scenarios is something I would never classify as "massive", in my book at least.
I know this is mostly enthusiast talk, but words kinda lose their meaning that way.

Upgrading from a 3600 to a 5800X3D (w/ a GA102 or N21 GPU), now that's what I call massive differences.

 

[Carfax83]

Well it seems your leaks were wrong

Wow, that's even worse than what I thought!

 

[PJVol]

Well, the default fclk is 1733, and doesn't run 1:1 with uclk and mclk

The more important is uclk and mclk is 1:1 and not 1:2 as was the case from async mode before. DF serving 2 ccd's and quite complex IO die is begged to have a separate DPM (which I believe has partially been implemented on Cezanne APU). The trick I think is in sync logic (latchups) at the clock domain transition between DF CS and UCLK/DFI

 

[Carfax83]

That's one of the reasons why Rocket Lake was no match for Zen 3 in games, despite having 10 ns better latency than Zen 3.

Exaggerate much? Zen 3 to me was indisputably superior to Rocket Lake, but saying the latter was no match is absurd.

Zen 3 was able to mitigate the latency penalty in games by having a massive L3 cache twice the capacity of the one in the 11900K and a much better branch predictor as well.