Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Doug S]

On ram latency, realize that, with healthy L3 caches and the increased L2 cache size, dram latency is reduced in importance. Yes, there will always be some impact, but we're splitting hairs here. First word latency is larger for DDR5 today, but, for a transfer of any appreciable size, DDR5 will complete the memory transfer before DDR4 does, even if it gets a few dozen cycles head start.

Depends on what the code is doing. If it does a lot of pointer chasing, that first word latency has a big impact. But yeah, for most workloads big caches are pretty good at hiding that.

 

[Just Benching]

The problem is AMD says AM5 Zen 4 sweet spot is 6000mhz. The way to overcome latency is with high speed ram. Does this mean the same memory divider problem will exist with Zen 4 as Zen 3 faces with speeds above 3800-4000mhz? The 1:1 memory divider issue.

I am not trying to jump the gun here but I am hearing 8000mhz DDR5 speeds have been achieved. There is DDR4 memory that can go above 5000mhz.

DDR4 above 5000mhz is no bueno. I mean sure, ram can do it, no IMC can, unless you run in GEAR 2, which defeats the purpose. The best IMC was on cometlake and even they struggled above 4400. Regarding DDR5, it seems 7000 is easily achievable with current alderlake and z690 mobos, above that no one knows




you want to post about cometlake and alderlake?
We have threads for those. Just not here.


esquared
Anandtech Forum Director

 

[igor_kavinski]

Regarding DDR5, it seems 7000 is easily achievable with current alderlake and z690 mobos, above that no one knows

MSI had to sacrifice everything to hit this 10,004MT/s DDR5 RAM overclock | PC Gamer

I didn't know that you could hit higher RAM speed by gimping the CPU. Any technical explanation, anyone?

 

[itsmydamnation]

The problem is AMD says AM5 Zen 4 sweet spot is 6000mhz. The way to overcome latency is with high speed ram. Does this mean the same memory divider problem will exist with Zen 4 as Zen 3 faces with speeds above 3800-4000mhz? The 1:1 memory divider issue.

I am not trying to jump the gun here but I am hearing 8000mhz DDR5 speeds have been achieved. There is DDR4 memory that can go above 5000mhz.

No , learn how memory works , it's access time measured in ns. So mem speed X cas latency ~= access time. So guess what magic exists , it's quite voodoo , you can trade mem speed for cas/other latencies.

So we can pretend it's a problem or join reality.

 

[Zucker2k]

MSI had to sacrifice everything to hit this 10,004MT/s DDR5 RAM overclock | PC Gamer

I didn't know that you could hit higher RAM speed by gimping the CPU. Any technical explanation, anyone?

It's fairly obvious, a gimped core won't make as demanding a call to the memory subsystem as a core running full tilt would. In the thin line where these sort of overclocks thrive, the slightest variation in power fluctuation can result in catastrophic consequences.

So, frequency here is everything - the more frequent calls the core makes to the memory subsystem, the more the stress it exerts on it, and the more likely that something would give.

 

[Hans de Vries]

A second Ryzen 9 7900X userbenchmark result really blows everything on the top list away

https://userbenchmark.com/UserRun/55296903

143% versus the 117% of the Ryzen 5 7600X from july. The average i9 12900KS scores 115%

 

[inf64]

A second Ryzen 9 7900X userbenchmark result really blows everything on the top list away

https://userbenchmark.com/UserRun/55296903

143% versus the 117% of the Ryzen 5 7600X from july. The average i9 12900KS scores 115%

I wonder what will tuned 7950X with DDR5-6000 score . It's going to be brutal end of the month for CPUpro guy... Day of reckoning has come for UB.

BTW they are filtering out both 7900X scores from the main CPU list(when sorted by average bench score):


They did leave the pejoratively named Zen4 hype train part in the list, but excluded retail 7900X scores.... These people are so weird.

 

[inf64]

Tum Apisak found 7950X on sisoft sandra:

https://twitter.com/x/status/1570699364133392384

Improvement % vs 5950X (by another twitter user):

Quad-float	50%
Double-float	64%
Single-float	80%
Quad-int	118%
Long-int	53%
Integer	104%

Details for Result ID AMD Ryzen 9 7950X 16-Core Processor (2M 16C 32T 5.75千兆赫（GHz）, 1.87千兆赫（GHz） IMC, 16x 1兆字节（MB） L2, 2x 32兆字节（MB） L3)

ranker.sisoftware.co.uk

 

[inf64]

For comparison, I found the 13900 ES numbers that Sisoft Sandra website published (and then pulled) on June 13 2022:

Intel 13th Gen Core RaptorLake (i9-13900) Preview & Benchmarks – Hybrid Performance – SiSoftware

web.archive.org

I don't know how final was this Raptor Lake ES and what clocks it ran at, so these numbers are not final.

 

[deasd]

For comparison, I found the 13900 ES numbers that Sisoft Sandra website published (and then pulled) on June 13 2022:

Intel 13th Gen Core RaptorLake (i9-13900) Preview & Benchmarks – Hybrid Performance – SiSoftware

web.archive.org

I don't know how final was this Raptor Lake ES and what clocks it ran at, so these numbers are not final.

View attachment 67643

12900/13900 in this graph are terrible cuz the E-core didn't work in heavy SIMD workload (>=256bit), and provide nearly 0 performance.

If we divide the 7950X result by 2, make them 8C to 8C comparison, we can see Zen4 IPC in this test is pretty comparable to GoldenCove, while Integer/Quad Int favor AMD a bit, GC win in Quad Float. We don't know what clock the 7950X was running so it's just a guess.

 

[Kaluan]

Nice!

The arithmetic ones shouldn't be far off from leaking either I guess.

 

[lightmanek]

So if Mike Clark is excited about Zen 5 and this Zen 4 core is just optimisation and balancing act between IPC and clock potential, then Zen 5 will be EPIC!!!

 

[igor_kavinski]

The CPU prices are worth it for the performance being seen. Regarding mobos, I guess the mobo manufacturers want to make enough for the work involved in creating the expected 5 to 6 years of BIOS updates.

 

[nicalandia]

Its beyond impressive how much Int performance those Zen4 CPUs have. How did the 7950X able to achieve over 100% boost on Integer performance?

 

[inf64]

Its beyond impressive how much Int performance those Zen4 CPUs have. How did the 7950X able to achieve over 100% boost on Integer performance?

I suspect that massively increased OP cache is the culprit for UserBenchmark's demise . It's simply too overpowering for their feeble "benchmarking" code. I expect a new benchmark revision soon to curb the massive performance jump we see in UB.

 

[naad]

Its beyond impressive how much Int performance those Zen4 CPUs have. How did the 7950X able to achieve over 100% boost on Integer performance?

Seems like the reorder buffer got increased by a good 40 entries IIRC, that along with a massive clock jump and improved branch predictor do nice for integer perf.

 

[coercitiv]

I expect a new benchmark revision soon to curb the massive performance jump we see in UB.

First they need to buy the chip, or loan one at least

 

[inf64]

First they need to buy the chip, or loan one at least

If UB benchmark is cache sensitive then imagine the meltdown when 3D version of Zen 4 results are in. It will be glorious sight!



5800X3D scores very similarly to 5800X despite the clock deficit, so bigger L3 plays some role.

 

[LightningZ71]

Oh, I expect them to look for a benchmark that has good residency in the larger L2 cache of Golden/Raptor cove but spills badly on Zen4's 1mb L2, then weigh it at 90%.

 

[Panino Manino]

So if Mike Clark is excited about Zen 5 and this Zen 4 core is just optimisation and balancing act between IPC and clock potential, then Zen 5 will be EPIC!!!

If he real world in your home performance remains too good to be true like this, this is the part that it's most unbelievable.
This is AMD doing a "low effort job" saving all the real good changes for the next Zen? Performance progress is accelerating this much? I'm not used to think about AMD being able to do this. Is this even possible? I can't deal with this anymore, these leaks are driving me crazy. I should stop coming here...
(and I hope that software will not become more demanding forcing me to make upgrades soon just to browse the web)

 

[DisEnchantment]

Oh, I expect them to look for a benchmark that has good residency in the larger L2 cache of Golden/Raptor cove but spills badly on Zen4's 1mb L2, then weigh it at 90%.

Not very complicated to update the benchmark

    unsigned int eax, ebx, ecx, edx;
    char buffer[16] = {0};
    __get_cpuid(0x00000000, &eax, &ebx, &ecx, &edx);
 
    buffer[0]  =  ebx & 0xff;
    buffer[1]  = (ebx >>  8) & 0xff;
    buffer[2]  = (ebx >> 16) & 0xff;
    buffer[3]  = (ebx >> 24) & 0xff;
    buffer[4]  = edx & 0xff;
    buffer[5]  = (edx >>  8) & 0xff;
    buffer[6]  = (edx >> 16) & 0xff;
    buffer[7]  = (edx >> 24) & 0xff;
    buffer[8]  = ecx & 0xff;
    buffer[9]  = (ecx >>  8) & 0xff;
    buffer[10] = (ecx >> 16) & 0xff;
    buffer[11] = (ecx >> 24) & 0xff;    

    std::string str(buffer);
    long totalScore = getCPUScore();
    if(str.compare("AuthenticAMD") == 0){
        totalScore *= 0.75;
    }
    return totalScore;

 

[StinkyPinky]

Those numbers seem too good to be true?

When can we expects reviews? If AMD have such a great chip you would hope they would allow early reviews to get the hype train rolling.

 

[inf64]

Those numbers seem too good to be true?

When can we expects reviews? If AMD have such a great chip you would hope they would allow early reviews to get the hype train rolling.

Not really. Zen 3 was a massive success in every aspect and review NDA was on the day products were launched. AMD allowed one day of buffer this time (review NDA liftoff is on 26th of Sept).

 

[Kaluan]

Oh, I expect them to look for a benchmark that has good residency in the larger L2 cache of Golden/Raptor cove but spills badly on Zen4's 1mb L2, then weigh it at 90%.

That would mean all their (yes "their", since they seem to think they work for Intel 🤣 ) Rocket Lake and Skylake-derivatives would take a nosedive in their charts. The cutoff point would probably need to be 1,25MB so as to at least keep Tiger and Alder Lake relevant 😅

Gee, it's so easy (and pathetic) to be a troll, no wonder the world is full of 'em.


BTW can someone help decode what the "1,33GHz" and "1,87GHz" IMC info listing in the Sandra Arithmetic/Multimedia leaks mean?

 

[nicalandia]

BTW can someone help decode what the "1,33GHz" and "1,87GHz" IMC info listing in the Sandra Arithmetic/Multimedia leaks mean?

IMC stands for integrated memory controller.

For example the IMC speed registered on a 3900X is 1.6Ghz, on the 5900X is 1.8Ghz and on the 7900X is 1.87Ghz