Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[jamescox]

I think because the IO die is such a large piece of silicon, AMD will be incentivized to make a cut-down version for Sienna. Their volumes are easily getting to the point where the unit cost savings will eclipse the cost of a separate tape out.

I was thinking that the best way to go about making varying sizes would be to make the IO die modular such that 2 or 4 of the same chip could be used rather than one big monolithic die. Stacked bridge chips could make that a lot better, so perhaps we will get something like that with Zen 5. They could make a cut down die for Siena. If they have a high defect rate on 6nm IO die, then just using salvage parts may make sense. Siena is supposed to be lower cost, but it is still going to be more expensive than desktop parts.

 

[nicalandia]

Double post...

 

[nicalandia]

Yes, but does AMD give the chiplet and cache per chiplet counts anywhere? Just trying to figure out where the inconsistency came from. It seems like the 9124 (16-core ) and 9224 (24-core) are both 4 chiplet devices just with 16 MB of L3 per chiplet rather than 32 MB.

AMD Has never given a Chiplet per SKU information

It will not be the first time AMD cuts the Total L3$ Per CCD/Chiplet

The EPYC 7453 is a 28C/56T Zen3 CPU with 4 CCDs with 64 MiB L3$ per CPU, which means that each CCD gets 16 MiB which is half of what Zen3 is capable of.

https://www.amd.com/en/product/10951

AMD EPYC 7453 Specs

Milan, 28 Cores, 56 Threads, 2.75 GHz, 225 W

www.techpowerup.com

 

[BorisTheBlade82]

I think because the IO die is such a large piece of silicon, AMD will be incentivized to make a cut-down version for Sienna. Their volumes are easily getting to the point where the unit cost savings will eclipse the cost of a separate tape out.

That is the beauty - one can spin that theory both ways 😉
The question is if the amount needed will be worth the upfront costs of a separate mask set which to my knowledge is in the tens of million Dollar region. But if they sell a lot of Siena and Threadrippers it might well be worth it.

 

[Tigerick]

I tend to believe Sienna going to use much smaller IOD (AdoredTV has mentioned 263mm2 for Genoa which is certainly wrong but could be for Sienna platform). And Sienna platform also reduces power TDP, memory channels, PCIe 5.0 & 3.0 and CXL, so new spin seems reasonable.

And don't worry about volume, Sienna Next with Zen5c most likely coming soon.

 

[Exist50]

I was thinking that the best way to go about making varying sizes would be to make the IO die modular such that 2 or 4 of the same chip could be used rather than one big monolithic die. Stacked bridge chips could make that a lot better, so perhaps we will get something like that with Zen 5. They could make a cut down die for Siena. If they have a high defect rate on 6nm IO die, then just using salvage parts may make sense. Siena is supposed to be lower cost, but it is still going to be more expensive than desktop parts.

That's an interesting proposal. Some overhead, but could be worth it for time to market etc. Though it does hinge on having a proportional lower PCIe lane count as well. I don't think AMD's actually disclosed that detail yet.

 

[jamescox]

That's an interesting proposal. Some overhead, but could be worth it for time to market etc. Though it does hinge on having a proportional lower PCIe lane count as well. I don't think AMD's actually disclosed that detail yet.

I was originally thinking of that since it is similar to what Apple did with their m1 max, which is essentially two APUs connected together by a silicon bridge. It would be great if AMD could do something similar, but I suspect that we may not get any stacking or bridge chips until Zen 5. If two APUs or two small IO die could be connected together, then that could have offered a very cheap way to scale the core count for higher end desktop or mobile parts.

I may not be up to date (haven’t had a lot of time recently), but I suspect that going forward, there will be a lot of overlap with GPUs and CPUs. For GPUs, I guess they are using infinity cache chips which are rumored to only be 16 or 32 MB in size. That would be a very small chiplet. I have seen some things saying that the infinity cache chiplets that go under the base die also include memory controllers. That would make a lot of sense since it decouples the memory controllers from the base die. They could use the same base die possibly across all of their products, just with different bridge chips for different memory types: GDDR, HBM, DDR. The HBM interface is actually a very small die area, so those could have larger cache in addition to acting as an embedded bridge to the HBM memory.

If you look at a block diagram of a crusher node here:

ORNL Publishes Overview of AMD-Powered 'Crusher' HPC System: 192 EPYC 'Trento' 64 Core CPUs, 1536 Instinct MI250X GPUs, 40 PFLOPs Horsepower

ORNL has published the overview of its Crusher system which is powered by AMD's Optimized 3rd Gen EPYC CPUs & Instinct MI250X GPUs.

wccftech.com

The gpu chiplet require a massive number of interconnect links. Going forward, all of those links may be put in a base die with the compute die stacked on top. So the base die would have an embedded silicon bridge to a neighboring die, possibly a number of GMI style links to connect to die that are too far away for silicon bridges, and some off package links for IO. They also need the interfaces to memory, possibly via infinity cache chiplet. Given such a base die and several different infinity cache / memory chiplets, they could stack anything on top; RDNA GPUs, cDNA GPUs, CPUs, FPGA, or other accelerators.

So, do we get any stacked chips or other exotic things with Zen 4? It seems unlikely that they would waste their time with Zen 5 probably going 2.5D and possibly 3D in near the future. I could see them possibly making a half size IO die, but that depends on how many regular IO die are not fully functional but salvageable. Given the incredible number of IO interfaces on the Genoa IO die, it wouldn’t surprise me if a lot of them are defective in some way. Bergamo likely just uses the same IO die as Genoa. It is a little disappointing that we are unlikely to see any stacking with Zen 4. We will see it in GPUs first, but that makes sense since GPUs need so much more bandwidth.

 

[jamescox]

I tend to believe Sienna going to use much smaller IOD (AdoredTV has mentioned 263mm2 for Genoa which is certainly wrong but could be for Sienna platform). And Sienna platform also reduces power TDP, memory channels, PCIe 5.0 & 3.0 and CXL, so new spin seems reasonable.

And don't worry about volume, Sienna Next with Zen5c most likely coming soon.

We already knew the Genoa die sizes a long time ago from the gigabyte leak (copied from hardwaretimes; first Google hit):

“The documents also contain information regarding Zen 4 die sizes, such as the CCD and IOD. As per the leaked data, the Zen 4 CCD will have a die size of 10.70 x 6.75mm (area:72.225mm2), while the IOD will be 24.79 x 16.0mm (area: 396.64mm2).”

That is very large, but given the number of interfaces, it seems likely that they would have a lot of defective but salvageable parts. Given the incredible performance of Genoa, they will be making a lot of them.

 

[Exist50]

The question is if the amount needed will be worth the upfront costs of a separate mask set which to my knowledge is in the tens of million Dollar region. But if they sell a lot of Siena and Threadrippers it might well be worth it.

I think that's an easy bet. I don't have data for N6 mask or wafer prices, but let's just assume Siena's IO die is half Genoa's. That's ~200mm2 of silicon. Order of magnitude, that's somewhere in the 10s of dollars range. Means they'd only need to ship O(millions) of units for it to make sense. Siena should easily be able to hit those numbers.

 

[Asterox]

Ok, 230$ is much beeter price as the cheapest CPU entry in AM5.

https://twitter.com/x/status/1593229467107102721

 

[Kaluan]

Ok, 230$ is much beeter price as the cheapest CPU entry in AM5.

https://twitter.com/x/status/1593229467107102721

Especially if they launch A620 mobos around that time as well.

IMHO, such prices (if at least somewhat accurate) also leave some room for a bit of X SKU price readjustment. Raphael-X needs that room too.

Speaking of the only X3D SKU we know for certain we'll see, the 8 core, I don't see 7700 at $330 and 7700/7800 X3D at $450 not completely destroying $400 7700X sales.

 

[coercitiv]

IMHO, such prices (if at least somewhat accurate) also leave some room for a bit of X SKU price readjustment.

They're already getting readjusted, out here in Eastern Europe the 7600X and 7700X can be had for the equivalent US price of ~$240 and ~$350 respectively.

 

[maddie]

Great, it seems companies are starting to adjust to the new economic realities. We all should understand what's happening.

 

[jpiniero]

Ouch. RIP AMD's client margins I guess.

Not even going to try Zen 4 on AM4 first?

 

[nicalandia]

Ouch. RIP AMD's client margins I guess.

Which are not much or the bulk of their margins.

They sell their Top Genoa for $11,000 and corporations are like: "Shut Up and Take My Money"

 

[Markfw]

Ouch. RIP AMD's client margins I guess.

Not even going to try Zen 4 on AM4 first?

Loosing a little is better than inventory sitting around. I just got my 3rd 7950x for $100 less than the first 2.

 

[maddie]

Ouch. RIP AMD's client margins I guess.

Not even going to try Zen 4 on AM4 first?

All firms client margins will be hit. Those with the best cost structures will be the winners. Which ones are they, do you think?

 

[Kaluan]

Loosing a little is better than inventory sitting around. I just got my 3rd 7950x for $100 less than the first 2.

Which won't be a thing on next restock anyway. Since AMD will sell them for less than the launch batch(es). At least I assume that will be the case.

Resellers, big or small, have seen worse, much worse. Especially from other chip giants. I wouldn't worry too much for AMD's client channels.

Edit: Or was this about AMD's margins? Why is that even a topic? lol
Are we just gonna pretend the economy is fine? Or that Intel isn't taking even more brutal cuts to their margins selling 25% bigger dies for almost the same price as the ones from one year ago, right out of the gate. Just weeks after industry sources said they will increase prices by 10-20%? 😂

 

[jpiniero]

All firms client margins will be hit. Those with the best cost structures will be the winners. Which ones are they, do you think?

Intel, ironically enough. If we are talking client parts.

 

[Harry_Wild]

Loosing a little is better than inventory sitting around. I just got my 3rd 7950x for $100 less than the first 2.

Hoping on a 65W 7950 to be release!

 

[Markfw]

Hoping on a 65W 7950 to be release!

why wait ? just set it to that in the bios. Mine is running 142 watt, and that took me all of one minute, including the boot !

 

[maddie]

Intel, ironically enough. If we are talking client parts.

No price adjustments from them then? Is this your prediction?

 

[jpiniero]

No price adjustments from them then? Is this your prediction?

If Intel were to 'cut prices' they would most likely just offer OEMs better deals and leave DIY alone.

 

[scineram]

None of you lot are buying from AMD but retailers. Remember this.

All firms client margins will be hit. Those with the best cost structures will be the winners. Which ones are they, do you think?

obviously Intel with cheap insider silicon and simple monolithic packaging. Raptor is a big chungus die though. AMD also clearly said they rather stop shipping to reduce channel inventory than compete on price.

 

[maddie]

None of you lot are buying from AMD but retailers. Remember this.

obviously Intel with cheap insider silicon and simple monolithic packaging. Raptor is a big chungus die though. AMD also clearly said they rather stop shipping to reduce channel inventory than compete on price.

Why do you think running your own fab with all the R&D costs included is always cheaper that outsourcing to a specialist? That is such a misguided belief I see repeated contiguously.

Well maybe all the firms just abandon client. Joking of course, but they will have to drop prices as we see happening. With major companies firing workers & consumers revaluing wants, the TAM is falling. That's a fact that cannot be dismissed.

Do we still don't understand what's happening?