Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Schmide]

If those scores are from the built in benchmarks, they have been shown as useless. The built in benchmarking tool was (at launch) giving out inaccurate numbers.

I don't know exactly where those screenshots come from but,

Hardware Unboxed goes out of their way to avoid using built in benchmarks.

 

[deasd]

I honestly admit that I would be surprised if AMD used Hybrid in the Low-Cost segment first. Maybe ADL-U is eating Rembrandt alive from a OEM cost/revenue proposal perspective.
Either way it sounds like a good idea to start with a monolithic design first in order to learn. Later on they might add mix'n'matched Zen4/5 and Zen4c CCDs.

If those scores are from the built in benchmarks, they have been shown as useless. The built in benchmarking tool was (at launch) giving out inaccurate numbers.

I would be surprised if AMD pursued the so called 'hybrid' or 'heterogeneous' strategy at all. They have no need to do so and keeping things simple means a single chip covers top to bottom. Zen4c is different because cloud providers will buy a ton of chips.

I strongly suspect that EPYC, Threadripper, and Ryzen will continue to share the same architecture along with the new high end mobile chips. THAT is how you bring costs down, improve profitability, and scale up in terms of performance.

Pretty funny you guys call Zen4+Zen4C a HYBRID thing.

Only if AMD feel extra pressure of E-core spam from Intel's xxxLake-S lineup. Since MeteorLake-S stays 16 E-core max, I don't think AMD has that pressure to use cloud/density optimized cores in HEDT. And I agree mobile is another story, Intel could crazily spam 2P+8E which would make AMD upset.

Anyway I would rather see official confirmation than a random anonymous or new user from internet.

 

[leoneazzurro]

포시포시 on Twitter: "Alright, @quasarzone shared about Zen4 X3D info. Let's summarize it." / Twitter

Interesting rumor about Zen4 X3D

If true, performance increase respect to the standard model could be higher than with Zen3D because there would be almost no clock speed regression.

 

[LightningZ71]

Pretty funny you guys call Zen4+Zen4C a HYBRID thing.

Only if AMD feel extra pressure of E-core spam from Intel's xxxLake-S lineup. Since MeteorLake-S stays 16 E-core max, I don't think AMD has that pressure to use cloud/density optimized cores in HEDT. And I agree mobile is another story, Intel could crazily spam 2P+8E which would make AMD upset.

Anyway I would rather see official confirmation than a random anonymous or new user from internet.

I'm still having a big problem with seeing a 2 X Zen4 + 4 X Zen4C layout as even approaching the utility of a hybrid setup. It seems that just using a 6 core CCX with 8MB of L3 would accomplish the same thing without the die area hit of trying to break up the power domains and isolate scheduling. Zen4C is supposed to be feature complete with the regular Zen4 cores, just connected to a smaller L3 and using a denser process. Trying to run them both on the same CCD would kill any process benefit. I could see maybe doing a stack of two die that are optimized for different densities, or a tightly coupled tiny MCM with two different die. Heck, I could see a modified Mendocino die mixed with a 2 core N4 die for a 2 Zen4 + 4 Zen2 solution. The Zen4 CCD could be optimized as much as possible for performance without being overly large and the Mendocino modification could be modified as much as possible for power. In low power mode, the SerDes link could be completely powered down, and when performance is needed, burn the power as needed. Since it's a lower end solution, AVX-512 compatibility could be disabled without affecting desirability of the product.

 

[Saylick]

포시포시 on Twitter: "Alright, @quasarzone shared about Zen4 X3D info. Let's summarize it." / Twitter

Interesting rumor about Zen4 X3D

If true, performance increase respect to the standard model could be higher than with Zen3D because there would be almost no clock speed regression.

Idk who this new leaker is (allegedly Greymon55's alt account or something), but...

https://twitter.com/x/status/1598731730546036756

 

[desrever]

why the heck is everyone just believing this new account?

 

[leoneazzurro]

That's why I wrote "IF" true.

 

[Kaluan]

why the heck is everyone just believing this new account?

Probably because 1. they say nothing that is unreasonable, 2. educated speculation already showed similar expectations and 3. we already had previous soft and hard leaks and info alluding towards similar things

Also, some people here vouched that they're not "just a rando" or troll. Which isn't to say that their info is 100% correct, but at least not malicious/clicks-driven.

 

[Abwx]

5800X3D use 70-74W in games while the 7700X is at 72-77W, so it s no wonder that a theorical 7700X3D would see about no clock regression, beside the CPU voltage, that is lower than in the 5800X3D, wont be a limiting factor due to the added cache.

AMD Ryzen 7000 im Test: So schnell sind 7950X und 7700X: Leistungsaufnahme und Effizienz

Ryzen 9 7950X & Ryzen 7 7700X im Test: Leistungsaufnahme und Effizienz / TDP und PPT steigen deutlich

www.computerbase.de

 

[BorisTheBlade82]

Probably because 1. they say nothing that is unreasonable, 2. educated speculation already showed similar expectations and 3. we already had previous soft and hard leaks and info alluding towards similar things

Also, some people here vouched that they're not "just a rando" or troll. Which isn't to say that their info is 100% correct, but at least not malicious/clicks-driven.

TBH, a mix of Zen4+Zen4c for low-cost is something that no one expected. Also there was only one single member vouching for credibility while at the same time refusing to give any reasoning.
In the bigger picture the information might pretty well be accurate. Until CES23 I will hold my breath.

 

[Kaluan]

TBH, a mix of Zen4+Zen4c for low-cost is something that no one expected. Also there was only one single member vouching for credibility while at the same time refusing to give any reasoning.
In the bigger picture the information might pretty well be accurate. Until CES23 I will hold my breath.

Well yeah, that one's the outlier. Heh

But WE DID KNOW "Little Phoenix" might be a thing tho. Just not about the potential heterogeneous config.

 

[Joe NYC]

I'm still having a big problem with seeing a 2 X Zen4 + 4 X Zen4C layout as even approaching the utility of a hybrid setup. It seems that just using a 6 core CCX with 8MB of L3 would accomplish the same thing without the die area hit of trying to break up the power domains and isolate scheduling. Zen4C is supposed to be feature complete with the regular Zen4 cores, just connected to a smaller L3 and using a denser process. Trying to run them both on the same CCD would kill any process benefit. I could see maybe doing a stack of two die that are optimized for different densities, or a tightly coupled tiny MCM with two different die. Heck, I could see a modified Mendocino die mixed with a 2 core N4 die for a 2 Zen4 + 4 Zen2 solution. The Zen4 CCD could be optimized as much as possible for performance without being overly large and the Mendocino modification could be modified as much as possible for power. In low power mode, the SerDes link could be completely powered down, and when performance is needed, burn the power as needed. Since it's a lower end solution, AVX-512 compatibility could be disabled without affecting desirability of the product.

I think this will be an extremely low end, low cost, low power, monolithic design. Probably well under 100 mm2

 

[Mopetar]

AMD already has Mendocino that just launched to cover the low end so I don't see where a 2C/4C fits in unless it won't be released for quite a while.

I don't think Zen 4c is so much more area efficient than Zen 4 that it makes sense for AMD to design a weird 2+4 core combination instead of just releasing a 4-core Zen 4 chip unless this is acting like some kind of pipe cleaner product for AMD as well.

Why not just release an 8-core Zen 4c APU instead?

 

[jpiniero]

Why not just release an 8-core Zen 4c APU instead?

FMax not high enough. Think of this like Alder-U.

 

[DrMrLordX]

Only if AMD feel extra pressure of E-core spam from Intel's xxxLake-S lineup. Since MeteorLake-S stays 16 E-core max

Where are you getting that there's gonna be a 16-core Crestmont implementation of Meteor Lake?

 

[HurleyBird]

Also, some people here vouched that they're not "just a rando" or troll. Which isn't to say that their info is 100% correct, but at least not malicious/clicks-driven.

Seems to be mostly just the one person. And when asked why we should trust this new leaker, silence.

 

[Kaluan]

Seems to be mostly just the one person. And when asked why we should trust this new leaker, silence.

It's not like people with the in on the industry and sources would just... give us the name of the AIB they work for or the way they get private information out. 😅

A level of secrecy is needed.
At the end of the day one can have all the proof in the world, they could still doubt it. So it's not like knowing for sure before official announcements are made is a thing.

Anyway, apparently old school people from the leak-o-sphere like 'momomo_us' are retweeting their leaks like candy. For whatever that's worth.

 

[LightningZ71]

AMD already has Mendocino that just launched to cover the low end so I don't see where a 2C/4C fits in unless it won't be released for quite a while.

I don't think Zen 4c is so much more area efficient than Zen 4 that it makes sense for AMD to design a weird 2+4 core combination instead of just releasing a 4-core Zen 4 chip unless this is acting like some kind of pipe cleaner product for AMD as well.

Why not just release an 8-core Zen 4c APU instead?

You mean like "big phoenix"? That has, essentially, an 8 core Zen4c ccx.

 

[deasd]

Where are you getting that there's gonna be a 16-core Crestmont implementation of Meteor Lake?

a one month old leak

北森瓦版 - “Meteor Lake-S”は6 P + 16 Eに“Arrow Lake-S”は8 P + 16 Eになる？

北森瓦版 - Northwood Blog (Author : 北森八雲. Since July 10, 2006.)

northwood.blog.fc2.com

Intel's Next-Gen Desktop Platform Intros Socket LGA1851, "Meteor Lake-S" to Feature 6P+16E Core Counts

Keeping up with the cadence of two generations of desktop processors per socket, Intel will turn the page of the current LGA1700, with the introduction of the new Socket LGA1851. The processor package will likely have the same dimensions as LGA1700, and the two sockets may share cooler...

www.techpowerup.com

Intel Desktop Meteor Lake-S CPUs To Feature Up To 22 Cores, Arrow Lake-S Up To 24 Cores, Quad Xe iGPU Cores & 125W TDPs

Intel's 14th Gen Meteor Lake-S & 15th Gen Arrow Lake-S Desktop CPU SKUs have been detailed for the next-gen LGA 1851 socket platform.

wccftech.com

　 Meteor Lake-S 22 (6 P-core + 16 E-core) + 4 Xe cores, TDP125W
　 Meteor Lake-S 22 (6 P-core + 16 E-core) + 4 Xe cores, TDP65W
　 Meteor Lake-S 22 (6 P-core + 16 E-core) + 4 Xe cores, TDP35W
　 Meteor Lake-S 14 (6 P-core + 8 E-core) + 4 Xe cores, TDP65W
　 Meteor Lake-S 14 (6 P-core + 8 E-core) + 4 Xe cores, TDP35W

 

[BorisTheBlade82]

It's not like people with the in on the industry and sources would just... give us the name of the AIB they work for or the way they get private information out. 😅

Of course, but just saying "Because I say so" sounds a bit arrogant, don't you think?

 

[DrMrLordX]

a one month old leak

Color me skeptical, but we'll see.

 

[Exist50]

You mean like "big phoenix"? That has, essentially, an 8 core Zen4c ccx.

No, that's normal Zen 4.

 

[moinmoin]

No, that's normal Zen 4.

That's the part about the "Big" and "Little" Phoenix leak that confuses me so far:
Previous mobile APUs never had the normal Zen cores but ones with significantly higher density and L3$ cut in half. That's what I expected Zen 4c to be about.

Now the leak talks about both Zen 4 and Zen 4c as part of PHX2, both with L3$ cut in half compared to the respective "normal" version. Both should still have higher density, especially Zen 4 as it has to be ported from N5 to N4 anyway.

But for it to make sense to include both Zen 4 and Zen 4c cores there needs to be a significant functional difference between the two that makes using one decisively advantageous over the other based on specific workloads. Significantly cut down FPU as previously discussed perhaps?

So instead increasing the TAM by using the mobile core in the cloud market, it appears the cloud core is a distinct core design, doubling the amount of core designs per Zen gen.

 

[TESKATLIPOKA]

PHX2 can't be monolithic, If It has Zen4 + Zen4c. Another thing is CCX.
Zen3,4 had a single 8core CCX, now we will have 2 pairs? One with 2 cores and the second with 4?
6 Zen 4 would do the same job without using up a lot of extra space.

That new guy looks trustworthy for me, doesn't look like he is Greymon55, but PHX2 is quite weird.

 

[Tigerick]

PHX2 can't be monolithic, If It has Zen4 + Zen4c. Another thing is CCX.
Zen3,4 had a single 8core CCX, now we will have 2 pairs? One with 2 cores and the second with 4?
6 Zen 4 would do the same job without using up a lot of extra space.

That new guy looks trustworthy for me, doesn't look like he is Greymon55, but PHX2 is quite weird.

Yeah, if you do rough calculation of GPU die size based on SP, it is around half of the size of PHX's GPU area. We don't know the exact die size of 2P+4E with 8MB L3, but should be half of PHX's CPU as well...