Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[coercitiv]

but amd has a massive node advantage like 48% density and smaller cells

Would you rather have AMD on the same Intel 7 node with higher power consumption at low clocks but improved dynamic scaling and possibly even higher clocks when power is cranked to the max?

Neither of the companies have get a free luch, both nodes have their perks and disadvantages.

 

[Kaluan]

AMD/TSMC's "custom 5nm" is no way, twice as dense, or loosely said twice as good as Intel's "7 Ultra", yet somehow that didn't stop AMD from engineering Zen4 cores to only be half the size of a RC one. And they can easily scale them past 8. That's the impressive part. Not that it beats RC IPC in this or that synthetic by 1-2%.

I'm pretty sure the clock speeds of the 7800x3D aren't artificially limited but rather the 7900X3D and 7950x3D have higher clock speeds because they have chiplets that don't have V-Cache, and are using those cores as their ST max frequency.

Was talking about the 5800X3D. It doesn't ever max the PPT, 5800X does in most heavy loads. Beyond just voltage limits and and heat thresholds considerations, 5800X3D is firmware clock capped. I doubt sporadic ST boosts to 4.475-4.525GHz would have broken the chip, but I guess AMD wanted to err on the extra cautious side.

No idea how 7800X3D (or the V-Cache chiplets of the R9 X3Ds) will function out of the box. But allowing some forms of tunning/OC this time may indicate 7800X3D's fmax could be > 5GHz.

 

[Henry swagger]

Would you rather have AMD on the same Intel 7 node with higher power consumption at low clocks but improved dynamic scaling and possibly even higher clocks when power is cranked to the max?

Neither of the companies have get a free luch, both nodes have their perks and disadvantages.

Nah.. if intel was on tsmc 5nm they would be way infront in efficiency

 

[Henry swagger]

And Intel has a massive Watts disadvantage.
Seems balanced to me.

Huh ? What do you mean .. are you trolling?

 

[moinmoin]

AMD/TSMC's "custom 5nm" is no way, twice as dense, or loosely said twice as good as Intel's "7 Ultra"

Just keep in mind that the max possible density a node enables doesn't equal the density that's then used for specific silicon designs. Especially high frequency designs traditionally often use loose densities to afford those high frequencies.

Intel's desktop chip traditionally are pretty low density, though Intel stopped sharing numbers several gens ago. Raphael seems to use quite a lot of transistors for unknown purposes, possibly to reach the high frequency. RDNA3 and Phoenix both appear to use surprisingly high density.

Huh ? What do you mean .. are you trolling?

Node doesn't affect performance directly. An older node can achieve high performance with more power consumption if designed accordingly. Denser nodes only affect performance if power usage is a limiting factor in the design and a denser design allows the same performance at lower power consumption.

 

[Markfw]

Nah.. if intel was on tsmc 5nm they would be way infront in efficiency

What makes you say that ? Aside from you worship Intel.

 

[Exist50]

The Dense SDRAM Libraries basically did that, the die space size is that of a 8MiB but it's a 16MiB in capacity.

There's no evidence for that particular change to Zen 4c.

 

[nicalandia]

There's no evidence for that particular change to Zen 4c.

The orinal designation of Zen4c Was actually Zen4D, Zen4D was for DENSE..! They still call it Stones-Dense

 

[Exist50]

The orinal designation of Zen4c Was actually Zen4D, Zen4D was for DENSE..! They still call it Stones-Dense

View attachment 74219

Who says that means their SRAM libraries are different? Much less 2x the density!

 

[nicalandia]

Who says that means their SRAM libraries are different? Much less 2x the density!

They manage to double the the density of the stacked cache(64MiB die area is about the same as the 32MiB on core) They are using the same HD Process on the L1/L2/L3 for the Zen4c

 

[Timorous]

They manage to double the the density of the stacked cache(64MiB die area is about the same as the 32MiB on core)

View attachment 74226

Oh would you look at that. HD is about as dense as Phoenix and HP is about as dense as a standard Z4 CCD.

 

[nicalandia]

Oh would you look at that. HD is about as dense as Phoenix and HP is about as dense as a standard Z4 CCD.

Just edited the post. The reference reference was a very generic info from TSCM, but we have hard evidence of AMD implementation of HD SRAM Cells on their CPUs, and that is the 3D V Cache. They basically double the density




They manage to put 64MiB on a 41 mm^2 area. 16 MiB would take about 10 mm^2

 

[Geddagod]

You do realize that the specint is within 0.5% and specfp(less important) is within 4%? That is margin of error stuff basically. For the amount of transistors they spewed in GC, it should be stomping Zen4, and not matching or beating it with 0-4% difference. And all of that is against Zen4 vanilla version.

I don't think you understand that Golden Cove is *not* a universally big core. It's front end is large, yes, but it has 75% the execution ports than Zen 3 and Zen 4. Intel is bottlenecked by its execution ports, which it should build on with RWC I suppose. I mean you could already guess this with the redwood cove die shot estimations by Locuza, when you look at the core area comparison, you see most of the parts, which didn't really change, shrink by a factor of like 35-40%, but then you look at the INT execution part of the core and see a smaller shrink of only 25%. FP on the other hand saw a shrink of the more standard 37% (The reason the entire core shrunk by only 25% is because of increased L2 cache, and potentially increased L1 cache as well). Zen 3 is similar in the sense is that it is a building block architecture, where zen 4 basically takes the zen 3 architectures resources as far as it could without adding a bunch of area by expanding the core width. And as AMD themselves said, expanding the core width adds performance, but the reason they didn't do it yet is that they don't think the added complexity and area is worth it to them yet.
I think AMD did plan it out better, by adding a bunch of execution resources and then building up the front end as they did, because I think they realized that it would make the "inbetween cores" more area/efficient, as I'm also pretty sure expanding the front end takes up more core area.
So the statement "Intel used a bunch of transistors in their architecture they should be beating Zen 4" sounds like just PR, because it's not relevant in any way except if it makes the core extremely bloated, and as I showed you in the area comparison of its competitor Zen 3, it really didn't. The cost of adding a bunch of transistors is clock speed, or cost, and in reality it has better perf/area than its predecessor, so cost is fine, it clocks higher than zen 3 and zen 4 with RPL, so that's fine, and so I don't really get your point?

 

[Geddagod]

Would you rather have AMD on the same Intel 7 node with higher power consumption at low clocks but improved dynamic scaling and possibly even higher clocks when power is cranked to the max?

Neither of the companies have get a free luch, both nodes have their perks and disadvantages.

I highly doubt Intel 7 has higher Fmax than AMD's TSMC 5nm, if AMD decides to customize it even more to hit higher frequency goals than it already has. I'm pretty sure GLC has more pipeline stages than Zen 4 too, which also helps it clock higher, and besides Zen 4 only clocks slightly lower than RPL despite the architectural advantage RPL seems to have. Someone double check me on the pipeline stage thing though.

 

[itsmydamnation]

I don't think you understand that Golden Cove is *not* a universally big core. It's front end is large, yes, but it has 75% the execution ports than Zen 3 and Zen 4. Intel is bottlenecked by its execution ports, which it should build on with RWC I suppose. I mean you could already guess this with the redwood cove die shot estimations by Locuza, when you look at the core area comparison, you see most of the parts, which didn't really change, shrink by a factor of like 35-40%, but then you look at the INT execution part of the core and see a smaller shrink of only 25%. FP on the other hand saw a shrink of the more standard 37% (The reason the entire core shrunk by only 25% is because of increased L2 cache, and potentially increased L1 cache as well). Zen 3 is similar in the sense is that it is a building block architecture, where zen 4 basically takes the zen 3 architectures resources as far as it could without adding a bunch of area by expanding the core width. And as AMD themselves said, expanding the core width adds performance, but the reason they didn't do it yet is that they don't think the added complexity and area is worth it to them yet.
I think AMD did plan it out better, by adding a bunch of execution resources and then building up the front end as they did, because I think they realized that it would make the "inbetween cores" more area/efficient, as I'm also pretty sure expanding the front end takes up more core area.
So the statement "Intel used a bunch of transistors in their architecture they should be beating Zen 4" sounds like just PR, because it's not relevant in any way except if it makes the core extremely bloated, and as I showed you in the area comparison of its competitor Zen 3, it really didn't. The cost of adding a bunch of transistors is clock speed, or cost, and in reality it has better perf/area than its predecessor, so cost is fine, it clocks higher than zen 3 and zen 4 with RPL, so that's fine, and so I don't really get your point?

Your completely wrong here, zen3 /4 only has 4 real execution ports at any one time ( number of read/write to prf) Intel has 5 as well as more load/store. Intel core is wider in execution then amds.

 

[Geddagod]

Actually you know what, let me put this "GLC arch is hilariously big and terrible compared to Zen 4" argument to rest.
Redwood Cove is essentially an optimized GLC. There might be some expansions on the execution end of the core which could lead to some marginal IPC gains, nothing the size of a "new" core ofcourse, but still...
But let's just ignore that. Let's say RWC has 0 IPC gains. It should also have higher mem support, which as shown by SPEC IPC testing by Raichu, higher mem support helps GLC/RPC IPC perf more than Zen 4 because of their different cache-layouts, but ignoring that too and pretending that has 0% IPC gains....
Let's look at the size of a "8C" RWC complex vs 8C Zen 4 complex, you see they are both ~70 mm^2. Yes you could shave off some uncore for Zen 4, around 10mm^2 infact, but you could also shave off a bit of uncore from the compute tile on MTL as well, but maybe you can even that out from the fact that small cores are slightly more area/efficient than P-cores...
So basically worst case you have Intel and AMD, on effectively similar nodes (Intel 4 has better logic density, TSMC 5nm has better SRAM density, AMD prob customized TSMC 5nm for better density for their needs too there), Zen 4 being like what, 15% more area efficient, while also having the same IPC and performing (based on RPL) ~10% worse ST (using the same parameters as Locuza analysis).
This is ignoring potential IPC gains from RWC arch +mem support, but also ignoring potential frequency regressions from Intel 4, which I see as unlikely considering Intel is ONLY focusing on HP cells on Intel 4, not confirmed if working on UHP cells but UHP only adds ~5%, maybe less IIRC, max freq.

 

[Geddagod]

Your completely wrong here, zen3 /4 only has 4 real execution ports at any one time ( number of read/write to prf) Intel has 5 as well as more load/store. Intel core is wider in execution then amds.

Cardyak Microarch cheat sheet (on his twitter bio), total execution ports RPC vs Zen 4 12 vs 16.
Edit: also chips and cheese claiming Intel is bottlenecked by execution ports more than AMD

 

[Geddagod]

Your completely wrong here, zen3 /4 only has 4 real execution ports at any one time ( number of read/write to prf) Intel has 5 as well as more load/store. Intel core is wider in execution then amds.

Also found it: chips and cheese article:
Zen 2, 3, and 4 all have two 256-bit FMA units and four 256-bit ALUs. At first this might seem unexciting. But in a lot of workloads, feeding the execution units is more important than having a lot of them. Against Intel, Zen 4 has competitive vector throughput already. Intel doesn’t have a significant throughput advantage unless we look at server variants of their architectures, which have an extra 512-bit FMA unit on port 5.

And Raichu did not test Golden Cove server variants I'm pretty sure (I don't think he had access to them regardless)
But then again that also changes the perf/area analysis as well, because of added mesh agents and I think AMX as well, so....

 

[Rigg]

As i see it, even if there are more games that run somewhat better on 13900k, thats not surprising, as Golden/Raptor Cove core is still stronger than Zen4 core, and the only outliers i am aware of, where the performance difference is 30 percent or more, are those Spider-Man games, which are made by the same studio, so i would be looking for problem in there. AFAIK the games are using proprietary Insomniac engine, that the original 2018? game ran on, and the Remastered and MM games added RT features onto it - so its possible such significant performance difference is down to some bug or specific coding favoring Intel CPUs.

With a big enough sample size of games Raptor and vanilla Zen 4 seem pretty evenly matched. It's not really hard to cherry pick examples that show either in a better light. I tend to think Spider-man is just a poorly optimized port of a console game that favors Intel. There are plenty of games where AMD has the upper hand like Horizon Zero Dawn or Battlefield V.

The 30% number is completely misleading . The memory configuration and resolution for that testing makes the data nearly useless IMO. It's not an invalid way to test necessarily, but it's also very far removed from reality. Nobody would (intentionally) configure either one of these platforms with JDEC timings and officially supported memory speeds to play their video games. 720p data on flagship CPU/GPU's in 2023 is kind of silly IMO. It's mildly interesting for teh science but not particularity relevant to how any reasonable person would use the tested hardware. With a much more realistic memory config at 1080p the 13900k is no where near 30% faster than a 7950x in spidey.

 

[itsmydamnation]

Cardyak Microarch cheat sheet (on his twitter bio), total execution ports RPC vs Zen 4 12 vs 16.
Edit: also chips and cheese claiming Intel is bottlenecked by execution ports more than AMD

Also found it: chips and cheese article:
Zen 2, 3, and 4 all have two 256-bit FMA units and four 256-bit ALUs. At first this might seem unexciting. But in a lot of workloads, feeding the execution units is more important than having a lot of them. Against Intel, Zen 4 has competitive vector throughput already. Intel doesn’t have a significant throughput advantage unless we look at server variants of their architectures, which have an extra 512-bit FMA unit on port 5.

And Raichu did not test Golden Cove server variants I'm pretty sure (I don't think he had access to them regardless)
But then again that also changes the perf/area analysis as well, because of added mesh agents and I think AMX as well, so....

man.....

So .....

1. separate integer and FP resources. approximately 0 workloads stress both at the same time , you know how like SPEC has separate FP and INT benchmarks.
2. when people talk IPC they are almost always talking integer / logic / branch etc operations
3. look at number of EXECUTION resources the two cores have
zen 4:
simple integer : 4
complex mul : 1
complex div: 1
Load/Store : 3

Golden cove:
simple integer : 5
complex mul : 1
complex div 1
load /store : 5

if you look at FP its a little more complex because intel have a dedicated low latency FADD/ALU unit + two FMA/ MISC units while AMD have 2 FADD ( slower then then fast intel ALU ) and two FMA units. But again golden cove has way more Load/Store resources.

Golden Cove is a significantly bigger core, its bigger in almost all ways.
bigger core local caches
bigger front end
bigger execution / more PRF ports ( please actual understand what this means before ignoring it like last time ! )
bigger ROB
bigger L/S

 

[Geddagod]

man.....

So .....

1. separate integer and FP resources. approximately 0 workloads stress both at the same time , you know how like SPEC has separate FP and INT benchmarks.
2. when people talk IPC they are almost always talking integer / logic / branch etc operations
3. look at number of EXECUTION resources the two cores have
zen 4:
simple integer : 4
complex mul : 1
complex div: 1
Load/Store : 3

Golden cove:
simple integer : 5
complex mul : 1
complex div 1
load /store : 5

if you look at FP its a little more complex because intel have a dedicated low latency FADD/ALU unit + two FMA/ MISC units while AMD have 2 FADD ( slower then then fast intel ALU ) and two FMA units. But again golden cove has way more Load/Store resources.

Golden Cove is a significantly bigger core, its bigger in almost all ways.
bigger core local caches
bigger front end
bigger execution / more PRF ports ( please actual understand what this means before ignoring it like last time ! )
bigger ROB
bigger L/S

The microarch cheat sheet column is quite literarily labelled "execution ports". So AMD has more execution ports not execution resources?
Ok I will make an addendum then- AMD has more execution PORTS (not resources) than Intel which allows them competitive execution throughput which also allows them to be much closer in performance without blowing up the front end.
Bigger in almost every way, Golden Cove still has parts that are smaller, which is why chips and cheese claims "Against Intel, Zen 4 has competitive vector throughput already. Intel doesn’t have a significant throughput advantage"

Overall though, my conclusion still doesn't change. RWC (GLC+) on a competitive node with AMD Zen 4 doesn't has, at worst, a 15% worse perf/area while also being more performant. GLC is not a hilariously bloated architecture as some here make it out to seem, at least client.
AMD targeted the backend more than Intel, which means that they have to build up the front end in their architectures more. Zen 4 does this, as is the main focus of Zen 5 by increasing core width. GLC mostly focused on the front end, which means they can optimize their massive front end resources and focus on increasing the execution of the massive capacity they have, which could also be gleamed by comparing the shrinkage of part-to-part subsection of GLC vs RWC from Intel 7 to Intel 4.

 

[Geddagod]

With a big enough sample size of games Raptor and vanilla Zen 4 seem pretty evenly matched. It's not really hard to cherry pick examples that show either in a better light. I tend to think Spider-man is just a poorly optimized port of a console game that favors Intel. There are plenty of games where AMD has the upper hand like Horizon Zero Dawn or Battlefield V.

The 30% number is completely misleading . The memory configuration and resolution for that testing makes the data nearly useless IMO. It's not an invalid way to test necessarily, but it's also very far removed from reality. Nobody would (intentionally) configure either one of these platforms with JDEC timings and officially supported memory speeds to play their video games. 720p data on flagship CPU/GPU's in 2023 is kind of silly IMO. It's mildly interesting for teh science but not particularity relevant to how any reasonable person would use the tested hardware. With a much more realistic memory config at 1080p the 13900k is no where near 30% faster than a 7950x in spidey.

You can't really have it both ways, either you test at low resolutions to see how CPUs perform to the fullest, or you should test at worst 1440p because that's what the vast majority of people who buy those CPUs (13900k or 7950x) will be using for gaming, 1440p and 4k with 4090s and 4080s. And a small subsection of pro E-sports player I suppose.
Also testing at lower resolutions helps you predict future CPU performance at lower resolutions. For example, with HWUB initial 12900k testing with a 3090, he found the 12900k to be 3% faster. But with the only improvement being moving to DDR 6400 vs 6000, and also using a 4090, the improvement became nearly 20%. Which also matched the 3Dcenter Meta Review gains of the 12900k vs 5950x which was a mix of 1080p and 720 testing IIRC.

 

[itsmydamnation]

The microarch cheat sheet column is quite literarily labelled "execution ports". So AMD has more execution ports not execution resources?
Ok I will make an addendum then- AMD has more execution PORTS (not resources) than Intel which allows them competitive execution throughput which also allows them to be much closer in performance without blowing up the front end.
Bigger in almost every way, Golden Cove still has parts that are smaller, which is why chips and cheese claims "Against Intel, Zen 4 has competitive vector throughput already. Intel doesn’t have a significant throughput advantage"

Overall though, my conclusion still doesn't change. RWC (GLC+) on a competitive node with AMD Zen 4 doesn't has, at worst, a 15% worse perf/area while also being more performant. GLC is not a hilariously bloated architecture as some here make it out to seem, at least client.
AMD targeted the backend more than Intel, which means that they have to build up the front end in their architectures more. Zen 4 does this, as is the main focus of Zen 5 by increasing core width. GLC mostly focused on the front end, which means they can optimize their massive front end resources and focus on increasing the execution of the massive capacity they have, which could also be gleamed by comparing the shrinkage of part-to-part subsection of GLC vs RWC from Intel 7 to Intel 4.

No your just flat out wrong , the backend of GC is larger in every way that matters. that's because you have to get data in and out of the PRF. remember the number 1 rule of all computing , moving data is hard, executing data is easy. the things that matters to sustained IPC in the execution engine of the core is number of Arithmetic units, number of Read/write PRF ports , PRF size and ROB size, of which GC has more in all cases.

The cost to have both a bigger PRF and an additional 2 read and 1 write port to the PRF is very large because you have to sustain the same latency.

The GC backend is significantly bigger because the things that actually cost power and area are larger by a non trivial amount.

edit: fixing dyslexic moment of every PRF being RPF.......

edit2: answer me this , why would intel have so much more capacity in load store queue , bytes cycle to L1D and L/S ports if it didnt also have more execution resources? load store is extremely complex with memory disambiguation and the large number of reads and write a cycle it can do to L1D per cycle. They just did it for fun ?

And no its not a future growth thing , because intel have kept it growing at the same rate they have grown ALU capacity over the years ( from 3 -> 4 ->5 )

 

[Geddagod]

No your just flat out wrong , the backend of GC is larger in every way that matters. that's because you have to get data in and out of the RFP. remember the number 1 rule of all computing , moving data is hard, executing data is easy. the things that matters to sustained IPC in the execution engine of the core is number of Arithmetic units, number of Read/write RFP ports , RFP size and ROB size, of which GC has more in all cases.

The cost to have both a bigger RFP and an additional 2 read and 1 write port to the RFP is very large because you have to sustain the same latency.

The GC backend is significantly bigger because the things that actually cost power and area and larger by a non trivial amount.

That's just flat out wrong, since the number of execution ports AMD has is larger, and I'm literarily quoting an established source when I state that the execution throughput of Zen 4 is roughly the same as GLC. For having a backend that is "larger in every way that matters" Intel is yet STILL more bottlenecked than AMD because their front end is disproportionally larger, ALSO according to chips and cheese.
And you could see this in the total performance as well.

 

[Geddagod]

No your just flat out wrong , the backend of GC is larger in every way that matters. that's because you have to get data in and out of the PRF. remember the number 1 rule of all computing , moving data is hard, executing data is easy. the things that matters to sustained IPC in the execution engine of the core is number of Arithmetic units, number of Read/write PRF ports , PRF size and ROB size, of which GC has more in all cases.

The cost to have both a bigger PRF and an additional 2 read and 1 write port to the PRF is very large because you have to sustain the same latency.

The GC backend is significantly bigger because the things that actually cost power and area are larger by a non trivial amount.

edit: fixing dyslexic moment of every PRF being RPF.......

edit2: answer me this , why would intel have so much more capacity in load store queue , bytes cycle to L1D and L/S ports if it didnt also have more execution resources? load store is extremely complex with memory disambiguation and the large number of reads and write a cycle it can do to L1D per cycle. They just did it for fun ?

And no its not a future growth thing , because intel have kept it growing at the same rate they have grown ALU capacity over the years ( from 3 -> 4 ->5 )

About your edits:
edit 2: Idk if you just didn't read my post which you are responding too, because I said, and quoting "AMD has more execution PORTS (not resources) than Intel which allows them competitive execution throughput"
Also yes, architectures aren't completely balanced right out of the gate. What?
It quite literarily is a future growth thing. What did they keep growing at the same rate as ALU capacity?
Idk what is with the passive aggressiveness too, like cmon dude chill, we are talking about CPU architecture not deciding the future of your country lmao.