Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[nicalandia]

Techspot RAM Speed review

AMD Ryzen 9 7950X3D Memory Scaling Benchmark

Pairing fast RAM with a top-end CPU is a logical choice, but what happens when that processor is a Ryzen 9 7950X3D with 128 MB of cache?...

www.techspot.com

 

[Hail The Brain Slug]

Techspot RAM Speed review

AMD Ryzen 9 7950X3D Memory Scaling Benchmark

Pairing fast RAM with a top-end CPU is a logical choice, but what happens when that processor is a Ryzen 9 7950X3D with 128 MB of cache?...

www.techspot.com

Interesting to see the 7950X3D looks to be quite a bit more RAM sensitive than the 5800X3D. I wonder if the V$ CCD is just more sensitive to RAM than last gen, or if it has to do with the other CCD being used sometimes.

 

[nicalandia]

Interesting to see the 7950X3D looks to be quite a bit more RAM sensitive than the 5800X3D. I wonder if the V$ CCD is just more sensitive to RAM than last gen, or if it has to do with the other CCD being used sometimes.

It's beating a 7200 RAM 13900K...

 

[DrMrLordX]

Interesting to see the 7950X3D looks to be quite a bit more RAM sensitive than the 5800X3D. I wonder if the V$ CCD is just more sensitive to RAM than last gen, or if it has to do with the other CCD being used sometimes.

It's probably affecting performance of the other CCD.

 

[nicalandia]

The 48 Core Genoa makes its debut on GB5

ASUSTeK COMPUTER INC. ESC4000A-E12 - Geekbench

Benchmark results for an ASUSTeK COMPUTER INC. ESC4000A-E12 with an AMD EPYC 9454 processor.

browser.geekbench.com

 

[Geddagod]

It's beating a 7200 RAM 13900K...

That... has nothing to do with it?
But idk if the 7800x3d even shows much more RAM sensitivity compared to the 5800X3D.
The highest zen 3 supports is 3200, and going to 3800 only gets you a gain of like 2%. Similarly, the highest ram speed supported for zen 4 is 5200, and going to 6000 (what AMD calls the sweet spot) gets you like 3%.

 

[Mopetar]

The highest zen 3 supports is 3200, and going to 3800 only gets you a gain of like 2%. Similarly, the highest ram speed supported for zen 4 is 5200, and going to 6000 (what AMD calls the sweet spot) gets you like 3%.

I don't know what benchmarks you're referring to, but the recent HUB testing shows that AMD gets pretty significant performance gains in most games from tuning the memory. Even we'll-tuned 5200 will beat poorly configured faster memory, but it's not reasonable to claim that Zen isn't sensitive to memory settings isn't really true.

 

[Geddagod]

I don't know what benchmarks you're referring to, but the recent HUB testing shows that AMD gets pretty significant performance gains in most games from tuning the memory. Even we'll-tuned 5200 will beat poorly configured faster memory, but it's not reasonable to claim that Zen isn't sensitive to memory settings isn't really true.

Also HWUB, I think? Techspot is HWUB's website right?
I'm referring to 5800x3d review, they tested both 3200 and 3800 ram speeds in their OG review. Like 2%.
The other review I'm talking about is their recent 7950X3D memory scaling article. It shows a 3 or 4%, I forget how much exactly, going from ddr5 5200 to ddr5 6000.
I'm specifically referring to the 3D parts btw, not base Zen 4 or base Zen 3. So 5800x3D and 7950X3D, not 5800x and 7950x.

 

[Markfw]

Also HWUB, I think? Techspot is HWUB's website right?
I'm referring to 5800x3d review, they tested both 3200 and 3800 ram speeds in their OG review. Like 2%.
The other review I'm talking about is their recent 7950X3D memory scaling article. It shows a 3 or 4%, I forget how much exactly, going from ddr5 5200 to ddr5 6000.
I'm specifically referring to the 3D parts btw, not base Zen 4 or base Zen 3. So 5800x3D and 7950X3D, not 5800x and 7950x.

And that benchmarking would involve games only ??? If so, no doubt on 3d parts. What about CB23 ??

 

[Geddagod]

And that benchmarking would involve games only ??? If so, no doubt on 3d parts. What about CB23 ??

Ye, the figures I cited was the average gaming tests. CB23 wasn't really reliant on mem speeds regardless of the CPU having 3D-cache or not, I thought?
Overall though I don't think Zen 43D is any more reliant on mem speeds than Zen 33D is, at least for gaming tasks.

 

[lightmanek]

Also HWUB, I think? Techspot is HWUB's website right?
I'm referring to 5800x3d review, they tested both 3200 and 3800 ram speeds in their OG review. Like 2%.
The other review I'm talking about is their recent 7950X3D memory scaling article. It shows a 3 or 4%, I forget how much exactly, going from ddr5 5200 to ddr5 6000.
I'm specifically referring to the 3D parts btw, not base Zen 4 or base Zen 3. So 5800x3D and 7950X3D, not 5800x and 7950x.

I think we are concentraiting too much on memory speed and forgetting absolute latency. It would be better to compare memory scailing between Zen3 and Zen4 3D models keeping absolute latency constant while increasing bandwidth and also decrese latency by keeping relative timing static and varying memory speed.

I suspect Zen4 X3D will scale better with lower latency compared to increased bandwidtch, especially in game workloads.

 

[Markfw]

Ye, the figures I cited was the average gaming tests. CB23 wasn't really reliant on mem speeds regardless of the CPU having 3D-cache or not, I thought?
Overall though I don't think Zen 43D is any more reliant on mem speeds than Zen 33D is, at least for gaming tasks.

My point is that gaming benefits from the big cache on 16 threads or less, where CB23 uses all 32 threads, and I bet memory speed helps the cores not on the big cache. So using all 32 threads should make more of a difference in memory improving speed. No so much as games make memory speed almost irrelevant with the 3d cache.

Note the above is my deduction, not proved (yet) in benchmarks.

 

[Mopetar]

I'm assuming cinebench is pretty tightly coded to work best with prevailing cache sizes. I don't think cache is a big deal beyond the minimum it expects and that most CPUs have. Maybe it's possible to leverage additional cache for more performance, but until that becomes standard, I don't think there's a lot of pressure or reason to pursue those avenues. Zen-3D is a very early adopter of something that I think will eventually become widely adopted, but most software isn't being built with it in mind. The big performance wins are happy coincidence, but there're a lot of products that could be modified to leverage that additional cache.

 

[Joe NYC]

Nice new details. Primarily on V-Cache, but a lot of info on process nodes, die sizes transistor density.

On V-Cache, it has incredible transistor density, even though it stayed on N7. Die size shrunk from 41 mm2 to 36 mm2, number of transistors remained the same but TSVs are more efficiently and densely placed.

Only signal TSVs in the L3 area and power TSVs now segregated and moved over to the L2 area. So the V-Cache now covers L3 and partially L2 as well.

There is also some info on IO dies for both server and client. Graphics is taking quite a bit of space, but that's space on N6 that does not have to use N5.

The V-Cache bandwidth increased from 2 TB/s to 2.5 TB/s and the overhead to access V-Cache is 4 clocks - which is not bad for L3. Also, AFAIK, this overhead is only applicable if the data is coming from V-Cache portion of L3, not all of L3 (from comments going back to 5800x3d).

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5 TB/s

New images of the I/O Die, too.

www.tomshardware.com

 

[Geddagod]

Nice new details. Primarily on V-Cache, but a lot of info on process nodes, die sizes transistor density.

On V-Cache, it has incredible transistor density, even though it stayed on N7. Die size shrunk from 41 mm2 to 36 mm2, number of transistors remained the same but TSVs are more efficiently and densely placed.

Only signal TSVs in the L3 area and power TSVs now segregated and moved over to the L2 area. So the V-Cache now covers L3 and partially L2 as well.

There is also some info on IO dies for both server and client. Graphics is taking quite a bit of space, but that's space on N6 that does not have to use N5.

The V-Cache bandwidth increased from 2 TB/s to 2.5 TB/s and the overhead to access V-Cache is 4 clocks - which is not bad for L3. Also, AFAIK, this overhead is only applicable if the data is coming from V-Cache portion of L3, not all of L3 (from comments going back to 5800x3d).

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5 TB/s

New images of the I/O Die, too.

www.tomshardware.com

I think the most impressive part from that article is that Zen 4 uses 5nm HD cells - 6T right is HD right? I thought HD cells can't scale up to the voltages Zen 4 uses...

 

[BorisTheBlade82]

Nice new details. Primarily on V-Cache, but a lot of info on process nodes, die sizes transistor density.

On V-Cache, it has incredible transistor density, even though it stayed on N7. Die size shrunk from 41 mm2 to 36 mm2, number of transistors remained the same but TSVs are more efficiently and densely placed.

Only signal TSVs in the L3 area and power TSVs now segregated and moved over to the L2 area. So the V-Cache now covers L3 and partially L2 as well.

There is also some info on IO dies for both server and client. Graphics is taking quite a bit of space, but that's space on N6 that does not have to use N5.

The V-Cache bandwidth increased from 2 TB/s to 2.5 TB/s and the overhead to access V-Cache is 4 clocks - which is not bad for L3. Also, AFAIK, this overhead is only applicable if the data is coming from V-Cache portion of L3, not all of L3 (from comments going back to 5800x3d).

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5 TB/s

New images of the I/O Die, too.

www.tomshardware.com

Finally the confirmation, that the cache-die from Zen4 is not exactly the same one as from Zen3.
Positively surprised and impressed, that they achieved 7nm-on-5nm SoIC. TSMC never stated this to be a possible variant (much to my surprise back then in 2021 or so).

https://twitter.com/x/status/1632142176476856320

 

[nicalandia]

Cinebench Numbers for EPYC Genoa 9554 64 cores and 9534 64 cores.

Epyc Genoa 9554 64C/128T, 87,000 Points, stock


Epyc Genoa 9534 64C/128T, 75,000 points stock

 

[Kaluan]

Interesting to see the 7950X3D looks to be quite a bit more RAM sensitive than the 5800X3D. I wonder if the V$ CCD is just more sensitive to RAM than last gen, or if it has to do with the other CCD being used sometimes.

That... has nothing to do with it?
But idk if the 7800x3d even shows much more RAM sensitivity compared to the 5800X3D.
The highest zen 3 supports is 3200, and going to 3800 only gets you a gain of like 2%. Similarly, the highest ram speed supported for zen 4 is 5200, and going to 6000 (what AMD calls the sweet spot) gets you like 3%.

My biggest gripe is that they didn't test 1R vs 2R. That's were 5800X3D saw the most consistent gains.

Followed by "no Infinity Fabric/RAM scaling testing"

But it's still somewhat useful data.

 

[nicalandia]

Seems like the ES sample run faster due to them having less restrictions on TDP so they can stretch their legs.

 

[Markfw]

Seems like the ES sample run faster due to them having less restrictions on TDP so they can stretch their legs.

View attachment 78036

I was thinking of getting a Genoa. They can be configured from 320 to 400 watt tdp. I was trying to find a heatsink that could do 400, and could not find one.

 

[nicalandia]

I was thinking of getting a Genoa. They can be configured from 320 to 400 watt tdp. I was trying to find a heatsink that could do 400, and could not find one.

Go water Cooler..

Dynatron L32 All-in-one 1U Server AMD Socket SP5 Liquid Cooler | eBay

1U Server & Up. CPU Socket.

www.ebay.com

 

[Markfw]

Go water Cooler..

Dynatron L32 All-in-one 1U Server AMD Socket SP5 Liquid Cooler | eBay

1U Server & Up. CPU Socket.

www.ebay.com

Thats 1U, those fans would drive me nuts ! This is 320 watts and at least 2u (doesn't say) https://www.newegg.com/p/13C-000S-0...sp5-_-13C-000S-000M7-_-Product&quicklink=true

 

[igor_kavinski]

I was trying to find a heatsink that could do 400, and could not find one.

They are supposed to exist: https://www.techpowerup.com/286815/amd-zen-4-am5-sp5-cpu-coolers-spotted

 

[Timorous]

Nice new details. Primarily on V-Cache, but a lot of info on process nodes, die sizes transistor density.

On V-Cache, it has incredible transistor density, even though it stayed on N7. Die size shrunk from 41 mm2 to 36 mm2, number of transistors remained the same but TSVs are more efficiently and densely placed.

Only signal TSVs in the L3 area and power TSVs now segregated and moved over to the L2 area. So the V-Cache now covers L3 and partially L2 as well.

There is also some info on IO dies for both server and client. Graphics is taking quite a bit of space, but that's space on N6 that does not have to use N5.

The V-Cache bandwidth increased from 2 TB/s to 2.5 TB/s and the overhead to access V-Cache is 4 clocks - which is not bad for L3. Also, AFAIK, this overhead is only applicable if the data is coming from V-Cache portion of L3, not all of L3 (from comments going back to 5800x3d).

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5 TB/s

New images of the I/O Die, too.

www.tomshardware.com

Interesting.

Z4 CCD is 99M xtors per mm but if you exclude the IO and focus just on the cores and the cache the density is around 118M xtors per mm.

If Z4c is 16c with 32MB L3 cache and probably 2 of those IO blocks then it will need 10.8B (~4.15Bx2 for 16 cores + 2.35B for 32MB L3 + 0.7B*2 for the CCX IO) transistors which to fit in say a Z3 sized CCD would need a density of around 135M transistors per mm. Given we know the logic scales better than the cache on N5 and the fact that the cache amount is staying fixed and the core count is rising could AMD manufacture it on the current N5 node they already use? If 8c + 32MB L3 is 118M xtors per mm then it is logical to think 16c + 32MB L3 would be denser just due to the change in the ratio of logic to cache.

 

[leoneazzurro]

On a side note, AMD announced a couple of days ago the availability of Dragon Range mobile CPUs, and ASUS showed up their gaming notebook line based on it:

AMD Ryzen 7045HX "Zen4" Dragon Range 16-core laptops hit retail starting at $1799 - VideoCardz.com

Only Asus at the moment launched its line, but Lenovo and Alienware are supposed to follow soon, and MSI lineup should come as well.
AMD also claims 10% advantage in gaming over the 13900HX.