Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[itsmydamnation]

So AMD announced 3D stacking of SRAM at their Computex Keynote. I'm guessing with a bunch more LLC, they can feasibly implement that virtualized micro-op cache. The best part is that it's essentially HBM SRAM, so not only is the hit rate and capacity improved, the bandwidth is much higher as well. Separate SRAM chiplets can be manufactured on separate wafers, which should be easy to produce as the dies are small and the yields for SRAM are quite good. This tech is worth double digit IPC by itself.

re the V mirco-op cache , i had the exact same thought
The question is what is the yield of the die to die bonding process.

But yes 40mm sq of sram should be very cheap, this matches one of the earlier patients amd has. What I want to know now is, has the CCD been designed for this from the start or is it a new CCD.

Also cooling the cores will also be an interesting question, what the impact of the added material over the cores themselves.

 

[misuspita]

Maybe some of the TSV's themselves can act as a cooling heat transfer pipes? Some thicker ones that go from bottom die straight to the metal cover of the chip?

 

[jpiniero]

What I want to know is why AMD mentioned Warhol (?) now, given that "starting production end of year" doesn't exactly sound like it's going to be released any time soon.

 

[DisEnchantment]

The patent for virtual uop cache was filed like a year ago so I don't expect to see that in Zen 4. Maybe later generations? It sounds very cool though. Being able to use regular caches to store decoded instructions.

Not saying this will make it in any actual design but original patent was filed in 2018, and was updated a year later in a new filing.

https://www.freepatentsonline.com/y2020/0019406.html

So AMD announced 3D stacking of SRAM at their Computex Keynote. I'm guessing with a bunch more LLC, they can feasibly implement that virtualized micro-op cache. The best part is that it's essentially HBM SRAM, so not only is the hit rate and capacity improved, the bandwidth is much higher as well. Separate SRAM chiplets can be manufactured on separate wafers, which should be easy to produce as the dies are small and the yields for SRAM are quite good. This tech is worth double digit IPC by itself.

That was very cool and unexpected indeed.

Lisa mentioned

and we're ready to start production on our highest end products with 3D Chiplets by the end of this year

Not sure if it is for Zen4 or some Zen3+. But End of the year means too late for Zen3 refresh because it would launch almost back to back with Zen4. Or Zen4 is end 2022.

Or could be a GPU.
Aldebaran is a GPU and should be in production by now according to the Linux commit messages and also Frontier is scheduled to go in operation next Quarter.
Chiplet RDNA3 is a bit ways off for production.
I don't know if she meant for CPU or GPU. But I think from the context she meant CPU.
I am inclined to think this tech is a Zen4 tech and Zen4 could be launching by Q2 2022.

 

[jpiniero]

Not sure if it is for Zen4 or some Zen3+. But End of the year means too late for Zen3 refresh because it would launch almost back to back with Zen4.

Ian's blog specifically mentions Zen 3. This product almost has to be Warhol. The rumors that Zen 4 isn't being released until the end of next year is probally true then, or at least the desktop products.

 

[Saylick]

Not sure if it is for Zen4 or some Zen3+. But End of the year means too late for Zen3 refresh because it would launch almost back to back with Zen4. Or Zen4 is end 2022.

Or could be a GPU.
Aldebaran is a GPU and should be in production by now according to the Linux commit messages and also Frontier is scheduled to go in operation next Quarter.
Chiplet RDNA3 is a bit ways off for production.
I don't know if she meant for CPU or GPU. But I think from the context she meant CPU.
I am inclined to think this tech is a Zen4 tech and Zen4 could be launching by Q2 2022.

I would be elated if Zen 4 has V-cache and it was coming out in Q2 2022, but I suspect that we might see it first on server chips (i.e. that Milan-X rumor) for very specific SKUs.

 

[eek2121]

Warhol with the vcache = this year, probably around the time Alder Lake rolls out
Zen 4 = next year

Intel should just quit. (🤣 not really, but they are getting beaten to death)

 

[gdansk]

Seems like a something designed for server parts to me, despite being demonstrated on a 5900X gaming. But who knows. The same +64MB CCD should work in both, right?

 

[eek2121]

Seems like a something designed for server parts to me, despite being demonstrated on a 5900X gaming. But who knows. The same +64MB CCD should work in both, right?

If it is working in a 5900X, you can bet dollars to donuts DYI will get it this year.

I mentioned some time ago that AMD would try to wait until Apple was off from N5 before they launched Zen 4. This is how they are going to pull it off.

 

[Rigg]

If it is working in a 5900X, you can bet dollars to donuts DYI will get it this year.

I mentioned some time ago that AMD would try to wait until Apple was off from N5 before they launched Zen 4. This is how they are going to pull it off.

Yeah, You don't use a game benchmark on a desktop part to display a technology advancement if you don't plan to target that market. I'd love to see a Zen 3 XT refresh with the vcache to go against alder lake at the end of the year on AM4 although the way she worded that comment about production makes me highly skeptical this will happen. If they did manage to pull it off on AM4 and Intel goes DDR5 only for ADL that would be a massive blunder for Intel.

 

[uzzi38]

This should REALLY have been obvious from the beginning given they showed games and not Milan-X today but it WILL be available for desktops.

Just only expect it in the r9 lineup.

https://twitter.com/x/status/1399617955844005891

 

[exquisitechar]

This should REALLY have been obvious from the beginning given they showed games and not Milan-X today but it WILL be available for desktops.

Just only expect it in the r9 lineup.

https://twitter.com/x/status/1399617955844005891

Wow, the rumors were spot on about these chips. Zen4 is going to be huge with this technology, new IOD, new core, etc.

When are we getting APUs with V-Cache?

 

[uzzi38]

Wow, the rumors were spot on about these chips. Zen4 is going to be huge with this technology, new IOD, new core, etc.

When are we getting APUs with V-Cache?

Unfortunately I don't think we'll see it soon on APUs, but I could very easily be wrong.

 

[Racan]

Well then the rumors of 30% IPC improvement for Zen 4 are not so outlandish after all. Dr. Lisa Su is playing 4D chess lol.

 

[randomhero]

Being captain obvious, this tech was long time cooking. This is probably how they won supercomputer contracts for DOE. And you dont just slap on extra silicon on existing design, it has to be planned for.
This thing is going in Frontier. Also, hyperscalers have samples for sure, maybe even working instances. And this will come to piss on Alderlake's parade in due time.

 

[misuspita]

When are we getting APUs with V-Cache?

If they could release a AM4 APU with this cache structure it would be marvelous (for me)

Having just bought a 4650G this would really be an worthy upgrade for my needs. Even a GPU-less design on AM4 would be fantastic. Practically tle best socket ever, having supported for 4 full generations (excavator through zen3+)

 

[A///]

I sure would love to be a fly on Intel's walls tomorrow morning to hear the collective grandiose F bombs that will be moaned and groaned out at this bit of news.

 

[jamescox]

Ian's blog specifically mentions Zen 3. This product almost has to be Warhol. The rumors that Zen 4 isn't being released until the end of next year is probally true then, or at least the desktop products.

Very weird. I have been expecting them to use stacked caches of some kind for quite a while, but I though that it was a Zen 4 design. I was speculating that this would allow them to make some very large cache versions for high end DB and HPC applications. It may also allow using a specialized process or an older process for making the caches efficiently. Before Rome, Intel still had some advantages with a monolithic 38.5 MB L3 cache. The 32 MB cache on Zen 3 went a long way. Going up to 32 L3 + 64 L4 or 96 L3 (not sure how it is arranged) really makes all Xeons low end.

This apparently was demoed on Zen 3 though. I wonder if the original Zen 3 had connectivity for the stacked cache chip or if it was added recently in the new stepping. They almost certainly had to add some design elements to Zen 3 from the start. The design is a bit odd with structural silicon covering the cpu cores since the stacked cache chip only appears to cover the existing 32 MB L3. Thermal conductivity of the silicon wouldn't be that good but it might not matter. It sounds like this may use TSMC's tech that allows chip stacking without micro-solder balls in between. I forget what it is called. There is an Anandtech article on TSMC's different 2.5D and 3D stacking technology. The top (actually bottom due to flip-chip) would need to be thinned down to expose the through silicon vias, so the thermal conductivity may not be that big of an issue due to how close the transistor layers are to the surface. They most likely need to use structural silicon to provide the same thermal expansion characteristics. If the pictures in the slides are accurate, I am wondering if there will be a full coverage cache chip with 128 MB capacity for very high end applications. This seems to make a Zen 3 derivative paired with an AM5 IO die a more likely product. If it is released, it doesn't seem like they would want to release it on AM4. It also doesn't seem like they would have showed it off it it isn't going to be an actual product.

 

[Gideon]

This apparently was demoed on Zen 3 though. I wonder if the original Zen 3 had connectivity for the stacked cache chip or if it was added recently in the new stepping. They almost certainly had to add some design elements to Zen 3 from the start. The design is a bit odd with structural silicon covering the cpu cores since the stacked cache chip only appears to cover the existing 32 MB L3. Thermal conductivity of the silicon wouldn't be that good but it might not matter. It sounds like this may use TSMC's tech that allows chip stacking without micro-solder balls in between. I forget what it is called. There is an Anandtech article on TSMC's different 2.5D and 3D stacking technology. The top (actually bottom due to flip-chip) would need to be thinned down to expose the through silicon vias, so the thermal conductivity may not be that big of an issue due to how close the transistor layers are to the surface. They most likely need to use structural silicon to provide the same thermal expansion characteristics. If the pictures in the slides are accurate, I am wondering if there will be a full coverage cache chip with 128 MB capacity for very high end applications. This seems to make a Zen 3 derivative paired with an AM5 IO die a more likely product. If it is released, it doesn't seem like they would want to release it on AM4. It also doesn't seem like they would have showed it off it it isn't going to be an actual product.

Yeah, it's called TSMC's Chip-on-Wafer tech according to Ian.

I do think we'll also see this on AM4. I mean they already have a 5900X equivalent chip through validation and testing that can run multitude of games with 15% speedup that they just demoed. Why not just make some high-end R9 products from it?

 

[jamescox]

Being captain obvious, this tech was long time cooking. This is probably how they won supercomputer contracts for DOE. And you dont just slap on extra silicon on existing design, it has to be planned for.
This thing is going in Frontier. Also, hyperscalers have samples for sure, maybe even working instances. And this will come to piss on Alderlake's parade in due time.

This may have been part of it, but Epyc has massive advantages in many other ways. Having something like 250 GB/s of IO bandwidth with 128 pci-express 4.0 links seems like it would have been the deciding factor. Even Nvidia ended up using Epyc for their DGX A100 systems since you they probably could not get pci-express 4.0 capable intel systems at the time and they may have had to use 4 sockets or something to support 8 A100 GPUs with Xeon processors. If they use only 2 links for cpu to cpu connectivity in Epyc, then they can get 160 pci-express links for direct connect of 8 GPUs and have 2 x16 available for infinband cards and other IO.

 

[A///]

While James makes great points on the enterprise sector, I can see this being excellent if Threadripper 5XXX comes with it. If not, it's something to look forward to in Zen 4. However, I don't believe R9 Ryzens will see this anytime soon. Maybe with Zen 5.

 

[Gideon]

Having something like 250 GB/s of IO bandwidth with 128 pci-express 4.0 links seems like it would have been the deciding factor.

That wasn't really true for this case.

Aurora was supposed to be ready earlier, was won by Intel and is being built with Sapphire Rapid chiplets that have PCIe 5.0, "Rambo cache" chiplets, HMB2 on package if needed (and it looks like similar unified-memory-space software). The problem is it's using micro-bumps for stacking (well it's also very late, but that wasn't certain when Frontier was announced). So if anything Intel had the I/O advantage.

There had to be some secret sauce in AMDs offerings to win Frontier like they did. This is certainly one key differentiator. Bear in mind the V-cache solution actually most likely has two layers (as it sits on top of 32MB L3 and is exactly as big on the same process). There is nothing stopping AMD from adding more layers for some server CPUs and I'm convinced now CDNA2 has this stacking as well.

And while all of this is only possible because of AMD's engineering prowess, keep in mind that this is also TSMC's win as much as it's AMDs. They're the only foundry that has anything like that ready in this time-frame. The hoops TSMC had to go through to make this work (and be producible at scale) are also enormous.

All in all ever since Zen 2 it looks like it's the trifecta of execution (Synopsis + AMD + TSMC) that is to be congratulated. AMD couldn't just do it alone.

 

[jamescox]

While James makes great points on the enterprise sector, I can see this being excellent if Threadripper 5XXX comes with it. If not, it's something to look forward to in Zen 4. However, I don't believe R9 Ryzens will see this anytime soon. Maybe with Zen 5.

They demoed this "5950x" with gaming benchmarks, so it seems it is coming to Ryzen parts somehow. If they paired it with AM5 for the real product, then I would expect it to actually be a Ryzen 9 6xxx part. It is a weird demo and it would be odd to show off a non-ThreadRipper prototype part and then never make a product based on it. These may not be that expensive to make. It is a tiny cache chip; they would get huge numbers of them per wafer.

 

[Gideon]

Another tweet by chiakokhua mentioning it must be 2 L3 dies stacked with servers going up to 4 (288MB):

https://twitter.com/x/status/1399671225434087424

Another interesting point is tht the TSV sites have been in the CCD from the start:

https://twitter.com/x/status/1399664821717569542

 

[uzzi38]

And it only gets crazier

https://twitter.com/x/status/1399671731112091649