Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[A///]

Indeed. Also shows once more how closely AMD apparently works with TSMC.

Indeed. I'm astonished that the structure had been there forever since Zen launched. In broad daylight for all to see.

 

[A///]

What is nuts is that many of us were expecting a Threadripper announcement. Instead we got an an Intel basher.

Mate, I'm not bashing on Intel here. I use Intel daily. Anyway, I was also hoping for a Threadripper announcement. I stayed up all night to watch the feed but I can't say I was disappointed!

Edit: Never mind that first sentence. I'm going back to bed. Clearly I'm still not 100% awake.

 

[randomhero]

One of you is saying 2Q22 for Zen 4, the other posted a vague statement of Q1, could you please clarify, RH?

Well, I am of opinion that you don't show something and then you don't sell it.So AMD will launch x3d Zen3 definitely. Also X570S motherboards should launch soon, too. So desktop release is, at least for me, imminent. When is the best time to do it? When you can one up competition. Intel will
be probably launching Alderlake DT in Q1 '22, so why not give them hard time and for little extra cost.
Secondly, AMD can sell Zen3 well into 2023 and still have competitive solution for "low end"(if one can 12 and 16 core Zen3 cpu call low end), and you have remember that there are tons of Zen3 compatible boards out there and new one sare going to be produced for quite a while .

 

[eek2121]

Assuming that this becomes a standard thing for their CCDs going forward, do we think that stacking cache on the die will allow AMD to significantly increase the transistor counts for their actual ZEN4 cores, perhaps allowing them to go a bit wider, add a bunch of FPU circuits to support AVX-512, etc, and have a reduced amount of L3 con the CCD itself? Perhaps keeping the 8 core CCX, but using only 16MB of L3 between them, which is heavily taken up by the virtual op cache, and a large 64MB+ L3 on the stacked cache dies?

That should go a long way towards solving a whole lot of performance and competitive feature limitations against their competition.

Likely not. They aren’t covering the cores with this. It is only going over the cache. That being said, I am curious as to what happens when they shrink the IO die.

I think they're being coy about timelines because they don't want to tank their current sales. Why would anyone in their right mind buy a 5900x right now knowing that 15% faster with 2x the cache is only a few months away? Also the fact that zen 3 has been designed with stacked cache in mind from the very beginning says a lot with how far they are in its development. Right now its their best play to take things slow and im sure we'll hear more the closer we get to alderlakes launch. Also id assume their main use for the cache chiplets is frontier. Theres a reason why they're demoing this technology on desktop chips first even though it seems like its best use is in graphics and datacenter; I bet this is partly due to NDAs.

Likely they are waiting to see where Alder Lake lands.

They demo'd a 5900X, not a 5950X. 35:46 mm:ss

I simply don't see it happening on anything before Zen 5 for mainstream, maybe Zen 4 next year. I can see it being used on Threadripper 5000 processors, though. I have faith in AMD releasing their products on time, but they also said these would be in their higher end products at first. That's a very generic statement that could cover swathes of products most consumers won't buy.

Intel's Q4 for Alderlake is equally open given it being a quarter, but knowing how ridiculous they've gotten over the years, I expect a post Christmas launch from them.

AMD has already stated that this is going into production this year. Zen 4 is not before next year. They clearly have Zen 3 silicon working with it now, so I can’t imagine we won’t see a Zen 3 release.

Games aren’t the only thing that will be improved. Video encoding will see a big increase as well.

 

[A///]

Zen 4 is not before next year.

Mind pointing out where I said it was coming this year?

In fact, this is what I said.

I simply don't see it happening on anything before Zen 5 for mainstream, maybe Zen 4 next year.

 

[uzzi38]

𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠 on Twitter: "Confirmed with AMD that V-Cache will be coming to Ryzen Zen 3 products, with production at end of year." / Twitter

Desktop Zen 3 w/V-cache confirmed.

 

[A///]

Well, I am of opinion that you don't show something and then you don't sell it.So AMD will launch x3d Zen3 definitely. Also X570S motherboards should launch soon, too. So desktop release is, at least for me, imminent. When is the best time to do it? When you can one up competition. Intel will

How does X570S play into this? Is it the fanless factor we're after here or better VRMs which are more board dependent than chipset dependent? The competition has nothing to one up and hasn't had anything realistic in years.

Did you forget Dr. Su said their higher end products would be the first to get by the end of the year? To me that says Epyc, then Threadripper, and only then will mainstream DT get it. DC margins are better than DT.

Secondly, AMD can sell Zen3 well into 2023 and still have competitive solution for "low end"(if one can 12 and 16 core Zen3 cpu call low end), and you have remember that there are tons of Zen3 compatible boards out there and new one sare going to be produced for quite a while .

It's not always core count. It's performance, too. There are six and eight core processors from Intel from roughly a decade ago in their HEDT class. I considered them high end then, I don't today. If by 2023, Zen 5 is somehow out later in the year or whatever AMD releases past Zen 4, it'll be miles faster than older products, especially at AMD's large advances each year.

 

[randomhero]

No suprise there!
Edit: Answer to uzzi38 post about ryzen with x3d cache...

 

[A///]

Edit: NM

 

[Panino Manino]

V-Cache gives Zen 3 +15% performance in games at least, which means that AMD is confident that Zen 4 next year will give us a jump in performance much greater than that? Maybe 25-30% over Zen 3 at least?
x86 performance is accelerating?

 

[A///]

V-Cache gives Zen 3 +15% performance in games at least, which means that AMD is confident that Zen 4 next year will give us a jump in performance much greater than that? Maybe 25-30% over Zen 3 at least?
x86 performance is accelerating?

Basing the Zen 2 > 3 overall performance increase of 29%, I want to say this new cache and a new node should shove it up to 35-40% over Zen 3. Now if it's that figure over this new Zen 3 + V-Cache... Lots of good things.

Availability is going to matter a lot.

 

[eek2121]

Mind pointing out where I said it was coming this year?

In fact, this is what I said.

AMD said it was coming later this year, and that Zen 4 wasn’t coming until next year, which means it launches with Zen 3, not Zen 4.

This lines up with nearly all the leaks of a Zen 3+ with drastically improved gaming performance.

 

[A///]

AMD said it was coming later this year, and that Zen 4 wasn’t coming until next year, which means it launches with Zen 3, not Zen 4.

This lines up with nearly all the leaks of a Zen 3+ with drastically improved gaming performance.

Correction: AMD said they'll be implementing it on their higher end products near the end of this year. You can quote Ian on this.

AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at 2 TB/sec

www.anandtech.com

AMD says that it has made great strides with the technology, and is set to put it into production with its highest-end processors by the end of the year. It wasn’t stated on what products it would be coming to, whether that was consumer or enterprise. Apropos of this, AMD has said that Zen 4 is set for launch in 2022.

 

[Gideon]

Ian also confirmed in the same post it's a single (denser) die not 2 stacks. Though AMDs server bios clearly shows that server cpus will have up to 4 stacks, enablable in 1, 2 and 4 stack configs in BIOS:

https://twitter.com/x/status/1399701274489151489

 

[randomhero]

How does X570S play into this? Is it the fanless factor we're after here or better VRMs which are more board dependent than chipset dependent? The competition has nothing to one up and hasn't had anything realistic in years.

Did you forget Dr. Su said their higher end products would be the first to get by the end of the year? To me that says Epyc, then Threadripper, and only then will mainstream DT get it. DC margins are better than DT.

It's not always core count. It's performance, too. There are six and eight core processors from Intel from roughly a decade ago in their HEDT class. I considered them high end then, I don't today. If by 2023, Zen 5 is somehow out later in the year or whatever AMD releases past Zen 4, it'll be miles faster than older products, especially at AMD's large advances each year.

If mobo makers are producing new mobo designs they are expecting to make a buck. So new mobos tell you that latest compatible CPU for those mobos will sell at least 4Q after release of said mobos. Which CPU(s) is/are that? Zen3 based, of course.

And I agree with you that core count isn't all that matters.Thing is Zen3 based cpus will still be high end in 2023,especially with this tech. They will literally be half generation from latest one which will be zen4.
Now, when zen5 comes out it will be low end, I agree.

 

[A///]

If mobo makers are producing new mobo designs they are expecting to make a buck. So new mobos tell you that latest compatible CPU for those mobos will sell at least 4Q after release of said mobos. Which CPU(s) is/are that? Zen3 based, of course.

X570 is fairly expensive if you want something good. Many opted for B550. It's in fact why a new revision of the B550 chipset is also in play. The cheapest X570 board I wanted with good quality was about 300 minus tax.

And I agree with you that core count isn't all that matters.Thing is Zen3 based cpus will still be high end in 2023,especially with this tech. They will literally be half generation from latest one which will be zen4.
Now, when zen5 comes out it will be low end, I agree.

True, especially if comparing AMD to Intel. If my basic estimate in #1358 is any bit true or even 10% generous, and such performance is gained in Zen 4 > 5 it should be one heck of a chip. I haven't been this excited over chip gains in about 25 years. But I also lead a boring life...

 

[DisEnchantment]

𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠 on Twitter: "Confirmed with AMD that V-Cache will be coming to Ryzen Zen 3 products, with production at end of year." / Twitter

Desktop Zen 3 w/V-cache confirmed.

Thanks, at least no more guessing for now. So basically the cache only change is all there is or there is something more?
I am really curious for us non gamers, if there is something improved with just a cache increase. There is nothing indicated outside of gaming in the presentation.
I have ran many tests on my 5950X for a number of applications which I use regularly by using the downcore per CCD and comparing it the results I get when disabling a CCD and the increased cache per core is not really giving noticable gains.

Which makes me wonder why they keep throwing so much cache at it.

 

[Asterox]

𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠 on Twitter: "Confirmed with AMD that V-Cache will be coming to Ryzen Zen 3 products, with production at end of year." / Twitter

Desktop Zen 3 w/V-cache confirmed.

That is very good but expected, so probably Zen3 or Zen3+ with V-Cache in AM4 and AM5 socket.

Page 16 - Discussion - AMD Cezanne/Zen 3 APU Speculation and Discussion

Page 16 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[LightningZ71]

They continue to throw tons of cache at "it" because of three things:

1) It is a place where they can show a competitive advantage. They can have "more" cache than their competitor, thus gaining a marketing advantage. That's largely just academic though.

2) AMD still has a bit of a latency and memory performance deficit as compared to Intel products in competing market segments. Throwing extra L3 cache at the problem means that more and more memory accesses stop in cache, and are able to demonstrate lower latency and higher throughput, on average, then their competitiors product.

3) there's an argument to be made that it will save on package power. Memory accesses that do not need to hit the IOD or the main memory bus will consume less power than ones that do. If you save on power there, you can spend it in other parts of the chip, like the CCD, or just not spend at all.

 

[misuspita]

https://twitter.com/x/status/1399766139769602058

Dr. Cutress confirmes what we suspected

 

[uzzi38]

V-Cache gives Zen 3 +15% performance in games at least, which means that AMD is confident that Zen 4 next year will give us a jump in performance much greater than that? Maybe 25-30% over Zen 3 at least?
x86 performance is accelerating?

Even without the cache one should significant IPC gains with Zen 4 yes. X3D is just the icing on the cake.

 

[misuspita]

https://twitter.com/x/status/1399770424658087941

And a few other details

 

[uzzi38]

Probably Frontier paid a lot of the upfront R&D, like they have been doing with a lot of their tech, being starved for money.

Frontier has absolutely nothing to do with Milan-X.

Trento =/= Milan-X. They're not even remotely the same at all.

 

[Ajay]

Likely not. They aren’t covering the cores with this. It is only going over the cache. That being said, I am curious as to what happens when they shrink the IO die.

The new die on top of the CCD will have to be the same size as the CCD to conduct heat away from the CCD. Pretty sure Ian mentioned something about AMD using blanks.

 

[jamescox]

The new die on top of the CCD will have to be the same size as the CCD to conduct heat away from the CCD. Pretty sure Ian mentioned something about AMD using blanks.

The cache die (single layer) sits on top of the existing L3 cache. It may be slightly larger, at least it looks that way in the sample Lisa is holding in the images. It is 64 MB in a single layer using a cache optimized version of 7 nm. It probably also has less logic than the L3 on the main die since it is probably almost entirely SRAM with the control logic mostly on the main die. There had to be a lot of logic already present for this in the original Zen 3. I suspect the recent rumors about a new stepping for a Zen 3 update was probably AMD getting this working. It was probably present, but not functional in original die. It has some filler silicon strips along the edges over the cores to make the height the same to contact the lid evenly. Those are structural silicon. It probably needs to be silicon to provide the same thermal expansion rates. Thermals are an issue, but the top of the die needs to be thinned down and the stacked chip is also very thin, so it may not be that much of a limitation. TSMC's stacking test also has much better thermal transfer than tech using micro-solder balls.

This is the anandtech page with the 2.5D nd 3D stacking that TSMC has been working on. I linked this several times here already since I expected it to be used fro Zen4. I guess this should have been under Zen3 speculation though.

3DFabric: The Home for TSMC’s 2.5D and 3D Stacking Roadmap

www.anandtech.com

The tech for the cache chip is likely TSMC-SoIC which has very good thermal conductivity. Ian just did an article on it:

AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at 2 TB/sec

www.anandtech.com

 

[maddie]

The new die on top of the CCD will have to be the same size as the CCD to conduct heat away from the CCD. Pretty sure Ian mentioned something about AMD using blanks.

The new cache die only covers the cache portion of the CCD.
Pure silicon blanks are used to cover the core sections on either side. So three "sub-chiplets"?

I assume that very low grade silicon blanks can be used for this as only thermals are involved and this is most likely cut from defective silicon that fail the quality needed for diffusing circuitry. If true, a nice touch to reduce costs as no fab needed.