Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Mopetar]

AMD has stated in the past that they targeted 40% gen-on-gen IPC jumps. This has been true for Excavator->Zen1 as they targeted 40%, and achieved 52%. Zen1-> Zen3 brought us 1.03(Zen1+) x 1.15(Zen2) x 1.19 (Zen3) ~= 1.41 or ~40% IPC jump, just as they planned. For Zen5 to achieve the same, it would need to have a massive 1.4 (Zen5 target)/ 1.1 (Zen4) = 1.27 or 27% IPC increase Vs vanilla Zen4 cores. It's not impossible, but it's hard to expect they will manage to gain so much even with a much wider core. Zen4 does look like a missed opportunity on the IPC front.

Given that we know Zen 5 is going to have a new front end, I don't think it will be as hard to get there. There isn't a lot more AMD can do with their current design because making a wider core with more ALUs is pointless if you can't issue enough instructions to keep the execution ports busy.

Making a better front-end probably necessitates changes to the L1/L2 instruction caches so those don't become a bottleneck either, which makes an improvements front-end a large project that can't just get by on incremental changes, at least not without those being largely pointless until all of the pieces come together.

See, all those "leaks" were exaggerated, and again, leakers creating unrealistic expectations resulting in unnecessary disappointment. Sometimes it feels like an on purpose psyops.

It's more a consequence of the people who report on leaks wanting sensational headlines that will generate clicks.

But let's suppose we're in a parallels universe where AMD did get ~20% IPC with Zen 4, but couldn't push the clock rates much beyond what we see with actual Zen 4 and the overall performance gains are identical.

Are we supposed to be happy (or not disappointed) now because the rumors were correct even though they yielded no additional performance?

I'm not sure why people are disappointed when we know what the actual performance gains are and they're still good, particularly in MT where the extra TDP can be utilized. I also think the gaming performance is going to be better than the average 8-10% IPC expectations people are posting. The fast single thread is also going to be huge since that's what bottlenecks many titles even to this day.

 

[JoeRambo]

I also think the gaming performance is going to be better than the average 8-10% IPC expectations people are posting. The fast single thread is also going to be huge since that's what bottlenecks many titles even to this day.

I am pretty much certain that with stock memory 5800X3D will beat the hell out of Zen4 in gaming and it will take Z4 + 3D cache to beat it finally. Just not enough performance increase to beat brute force power of 96MB of L3.
What is really interesting, is how far they will be able to clock the chip with 3D stacked cache on top of it. Power density has increased, clocks have risen, might struggle to gain much over Z3 X3D incarnation, leaving just IPC gains + several hundred mhz.

 

[nicalandia]

I am pretty much certain that with stock memory 5800X3D will beat the hell out of Zen4 in gaming.

No chance in Hell that neither 5800X3D nor a 12900K/KS will "Beat the Hell" out of Zen4. Come on dude Really? You can't be serious.

 

[gdansk]

I doubt 5800X3D will be ahead on average. Certain games, yes. But many games will benefit from Zen 4's cache arrangement and clock rate increase too.

I expect top end Zen 4 gaming chip to be 8±3% faster over a reasonable assortment of games when equipped with high-end DDR 5 memory.

Based entirely on bad napkin math.

 

[JoeRambo]

I doubt 5800X3D will be ahead on average. Certain games, yes. But many games will benefit from Zen 4's cache arrangement and clock rate increase too.

I expect top end Zen 4 gaming chip to be 8±3% faster over a reasonable assortment of games when equipped with high-end DDR 5 memory.

Based entirely on bad napkin math.

I was talking stock ofc, and average as well as there are games where 5800x beats x3d chip due to clock speeds.

Z4 is still chiplets and it remains to be seen how good their first DDR5 IMC is. Intel's struggles with latency might not apply to them, but latencies will be interesting.

There is also a question of efficiency, if Z4 takes more power to match 5800x3d, it's not much of victory?

 

[Asterox]

I am pretty much certain that with stock memory 5800X3D will beat the hell out of Zen4 in gaming and it will take Z4 + 3D cache to beat it finally. Just not enough performance increase to beat brute force power of 96MB of L3.
What is really interesting, is how far they will be able to clock the chip with 3D stacked cache on top of it. Power density has increased, clocks have risen, might struggle to gain much over Z3 X3D incarnation, leaving just IPC gains + several hundred mhz.

I wouldn't be so sure, or in gaming there will be unexpected results in favor of Zen 4.

Do not forget, Zen 4 still has twice as big L2 Cache vs Zen 3+3D V-Cache.This is big change, if we consider the speed and bandwidth of L2 vs L3 Cache.

 

[Atari2600]

Intel R&D is now only about 4.3x AMD, and AMD is fabless. Just 3 years ago Intel budget was almost 10x. The difference isn't that big anymore and it's only getting smaller.

Wow, I did not realise the gap had shrunk that much!

Intel is also off chasing rainbows with its numerous missteps. [Optane anyone?]

In addition, its far easier to go from a small agile operation to a larger one and maintain performance. Whereas arresting and redirecting the inertia of a large cumbersome behemoth is a titanic task.

 

[nicalandia]

I wouldn't be so sure, or in gaming there will be unexpected results in favor of Zen 4.
.

Don't feed the troll

Whoever think 5800X3D and 12900KS will Beat the Hell Out of Zen4 at gaming(Mind you while gaming at excess speeds of 5Ghz) it's either mentally challenged or Trolling.

 

[JoeRambo]

Do not forget, Zen 4 still has twice as big L2 Cache vs Zen 3+3D V-Cache.This is big change, if we consider the speed and bandwidth of L2 vs L3 Cache.

Games usually scale the best with L3 cache size and memory latency. There is a valid question of where AMD's DDR5 latency will land, as their Zen3 DDR4 controller was really tight. There were some rumours about internal FClock being really high, so it might be 2600 or 2800mhz at stock.
We'll see when it lands. What is strange is that their IPC average of 8-10% includes SPEC int/FP and GB5 and these have subtests that should love DDR5 and reworked FP/VEC. Could be a case of outlier cancelling each other out.

Looking forward to first GB5 leaks, will be fun too look at subtests. And of course hoping for Anandtech to continue SPEC testing the chips.

 

[DrMrLordX]

Apples and oranges. You cannot currently install a GPU in an ARM based Mac, except possibly an external one.

Right, but currently if you are a performance user that will spend thousands of dollars on your PC and are at least passingly aware of the hardware capabilities you'll be getting when you spend that money, you want a dGPU that you can swap out depending on market conditions. Unless we go through another dGPU drought where buying one becomes prohibitively expensive, I do not expect most performance PC users to want a big APU, just the same way an M1 Ultra user can't effectively use a dGPU (and therefore doesn't really want one, since why else would they lock themselves in to the Mac experience?).

So is Siena going to be the base for that Zen4 Threadripper then?

Probably not. Siena seems to be going after Intel's comm equipment, which is a little weird since most of that stuff is low power/ultra low power. Stuff like Snow Ridge. Unless I'm missing something.

 

[nicalandia]

Probably not. Siena seems to be going after Intel's comm equipment, which is a little weird since most of that stuff is low power/ultra low power. Stuff like Snow Ridge. Unless I'm missing something.

How many Atom Cores(Intel just released a 20C/20T Atom core for that segment) does it take to match a low clock and low power 64C/128T Zen4 based Siena? I think they are going for Consolidation and centralization.

 

[LightningZ71]

I think people are missing something else important with this core update. SMT should improve by a good bit (still won't be massive overall, but a nice bump). With the widening of some parts of the core(I may have this confused with Zen5) , and the doubling of the L2 cache (to allow both threads to have twice the cache that they used to), the core's instruction throughput should improve notably for two simultaneous active threads. One of the roadblocks to good SMT performance in the higher core count parts was also limitations on memory concurrency and overall bandwidth, two things that DDR5 should give nice improvements on. I suspect that the MT improvements in some cases will be beyond a lot of expectations. You have so many things that have been done to improve MT, from memory improvements, more L2, some widening of parts of the core(again, may be confused with Zen5), and an overall larger power budget on a more efficient process, that I think that, even with 8 more E cores, Intel still won't take the overall MT lead with their 8+16 (32T) part against AMD's 16(32) part when they couldn't do it in the previous generation's 8+8 (24t) part against AMD's previous generation 16(32) part.

 

[DrMrLordX]

How many Atom Cores(Intel just released a 20C/20T Atom core for that segment) does it take to match a low clock and low power 64C/128T Zen4 based Siena? I think they are going for Consolidation and centralization.

A lot. It depends on how many of those you need per device, or how many devices you need per installation. I don't know much about the equipment where Intel's comm-class Atoms are installed, but my impression that a lot of that stuff goes into cabinets that don't necessarily have good airflow and may feature other unfavorable conditions, which is where you want your power dissipation kept low. That would be an environment that AMD hasn't tackled with their enterprise-class gear in the past.

 

[nicalandia]

A lot. It depends on how many of those you need per device, or how many devices you need per installation. I don't know much about the equipment where Intel's comm-class Atoms are installed, but my impression that a lot of that stuff goes into cabinets that don't necessarily have good airflow and may feature other unfavorable conditions, which is where you want your power dissipation kept low. That would be an environment that AMD hasn't tackled with their enterprise-class gear in the past.

Both products Intel Atom P and now AMD Siena target the Edge Computing/5G Telco segment, but they are design for different jobs.

The low power low maintenance Atoms are design for 5G base transceiver stations.

AMD Siena will Challenge Ice Lake or Sapphire Based High End Edge Computing with Racks like this one:




So AMD with Siena is aiming at the High End of the Processing power while providing lower TCO than Xeon Scalable products

 

[PJVol]

Oh well, it seems it is not just FP but int PPC improvements are pretty mediocre.
~2 years cadence, node advantage, tons of Xtor and this is all they manage.

Honestly, I wonder how they even managed to squeeze those 8-10% given the front-end and execution engine presumably haven't changed significantly.
Though the DF performance is still a mistery for me.

 

[moinmoin]

While Siena was introduced as a "lower cost platform" "optimized for intelligent edge and telco", having "optimized performance-per-watt", I can imagine it also being a first experimental platform for mixing and matching chiplets as AMD showcased elsewhere:

 

[nicalandia]

While Siena was introduced as a "lower cost platform" "optimized for intelligent edge and telco", having "optimized performance-per-watt", I can imagine it also being a first experimental platform for mixing and matching chiplets as AMD showcased elsewhere:

I highly doubt that, it's just a 64C/128T Zen4 with low clocks and less features than Genoa(there will be a 64 Core Genoa with Full features)

 

[Anhiel]

I think people are missing something else important with this core update. SMT should improve by a good bit (still won't be massive overall, but a nice bump). With the widening of some parts of the core(I may have this confused with Zen5) , and the doubling of the L2 cache (to allow both threads to have twice the cache that they used to), the core's instruction throughput should improve notably for two simultaneous active threads. One of the roadblocks to good SMT performance in the higher core count parts was also limitations on memory concurrency and overall bandwidth, two things that DDR5 should give nice improvements on. I suspect that the MT improvements in some cases will be beyond a lot of expectations. You have so many things that have been done to improve MT, from memory improvements, more L2, some widening of parts of the core(again, may be confused with Zen5), and an overall larger power budget on a more efficient process, that I think that, even with 8 more E cores, Intel still won't take the overall MT lead with their 8+16 (32T) part against AMD's 16(32) part when they couldn't do it in the previous generation's 8+8 (24t) part against AMD's previous generation 16(32) part.

I think you are mixing up things here. Google says it was MLID: https://www.hardwaretimes.com/amd-r...kloads-ddr5-pcie-gen-5-and-5ghz-boost-report/
So it was about back end not front end.

Anyhow, I don't think so regarding SMT. From what I see Intel's Sandy Bridge SMT has been consistent up to ADL and including RPL if my calculations are correct. The same goes with Zen's SMT up to Zen4. The average ratio remains very consistently the same for each architecture line.
The gains and details for Zen4 seem to match the claims for Rembrandt including the detail improvements. With the wider back end Zen4 should gain more when it comes down to calculations and some circumstantial code chains. These are probably tied to the added AVX512. Ordinary applications probably won't get more out of these.

 

[moinmoin]

I highly doubt that, it's just a 64C/128T Zen4 with low clocks and less features than Genoa(there will be a 64 Core Genoa with Full features)

I highly doubt that takes them until 2023 to realize and makes them fit "telco" as target audience. AMD so far lacks a flexible platform to realize what the slide I quoted implies, and this one based on a tweaked SP3 gives sufficient space while being lower cost than the bleeding edge platform Genoa and Bergamo use.

 

[jpiniero]

I highly doubt that takes them until 2023 to realize and makes them fit "telco" as target audience. AMD so far lacks a flexible platform to realize what the slide I quoted implies, and this one based on a tweaked SP3 gives sufficient space while being lower cost than the bleeding edge platform Genoa and Bergamo use.

Sienna is probably just that 6 (?) channel platform that's been rumored.

 

[PJVol]

Geekbench were on the lower end of the scale in Zen3's case.

Really? )

Spoiler

5600X PBO mimic 3600X stock settings, i.e. 128/80/125 x1 Fmax 4400Mhz

Generic vs Generic - Geekbench

 

[DisEnchantment]

I'm not sure why people are disappointed when we know what the actual performance gains are and they're still good, particularly in MT where the extra TDP can be utilized. I also think the gaming performance is going to be better than the average 8-10% IPC expectations people are posting. The fast single thread is also going to be huge since that's what bottlenecks many titles even to this day.

Many people do engineering work on their PC (surprise ), and x% faster = y secs/min/hours lesser time at doing something which over course of the day means a lot.
Since workload complexity grows with time, buying new faster HW regularly is always a good thing to improve productivity, so the improvement has to be substantial enough for the upgrade to be worth its while. More is always better.

But the frequency gains are very large indeed and 20% ST uplift on average seems within reach.
8% PPC * 12% Frequency = ~ 20% ST uplift

No wonder Mike Clark was already alluding to this, they already hinted one year ago and it just wasn't very obvious then

MC: I think IPC gets all the glory! What it really is – I call it the ‘Wheel of Performance’ because there's four main tenets – performance, frequency, area and power. They really are all equal in a sense and you have to balance them all out to get a good design. So if you go for a really high frequency but crush IPC, you can end up with a really bad design, and increased area. If you go really hard on IPC and that adds a lot of area and a lot of power, you can be going backwards. So that's really the critical part like we said, we're trying to get that IPC but we have to get it in a way that optimizes the transistor use for both area and power, and frequency too. We want to be able to put a bunch of cores in and just add IPC and grow area, we're not making real progress.

AnandTech Interviews Mike Clark, AMD’s Chief Architect of Zen

www.anandtech.com

 

[szrpx]

Games usually scale the best with L3 cache size and memory latency. There is a valid question of where AMD's DDR5 latency will land, as their Zen3 DDR4 controller was really tight. There were some rumours about internal FClock being really high, so it might be 2600 or 2800mhz at stock.
We'll see when it lands. What is strange is that their IPC average of 8-10% includes SPEC int/FP and GB5 and these have subtests that should love DDR5 and reworked FP/VEC. Could be a case of outlier cancelling each other out.

Looking forward to first GB5 leaks, will be fun too look at subtests. And of course hoping for Anandtech to continue SPEC testing the chips.

AMD has technically already made several DDR5 memory controllers, if you look at mobile.

 

[jamescox]

As much as I like amd. Zen's success is largely due to intel 10nm delays and intel culture. As there has been no report of of any drama plus intel's fabs getting on track, it is very possible for intel to win the long race. Normally it takes 4-5 years to realize one's vison, that coincides with lunar lake/ royal cove leaks thus far.

Not that I'm saying amd is doom, it's that intel's current delays are not the delays of the past.

There is always a bunch of stuff about the empire striking back, which was true previously, but isn’t actually true any more. Intel will have a tough time surpassing AMD. Even if Intel had executed much better, they would still have needed to accelerate there plans significantly, because of ARM. I read a phoronix review a while ago (Linux server and HPC) where it was AMD and ARM trading blows and Intel in third place for some benchmarks. There were still a few that Intel could win, but not many. I suspect that will be near zero after Genoa hits. Bergamo seems to be aimed more at ARM competitors than Intel.

Why is it different now? It is different because this isn’t AMD vs. Intel. This is AMD + TSMC vs. Intel. TSMC holds more than 50% of the semiconductor market. By breaking the Intel monopoly, we may actually be creating another monopoly on the fab side. Anyway, thinking that Intel will suddenly be able to dominate again is likely just not true. A large part of their previous market domination was due to better process tech than the competition. I am fine with intel not making a strong comeback yet since to really break the intel monopoly requires AMD to dominate for a bit longer. It would be great if AMD (or Intel) can nock Nvidia down a bit also, but the cuda vendor lock-in is strong.

 

[jamescox]

As much as I like amd. Zen's success is largely due to intel 10nm delays and intel culture. As there has been no report of of any drama plus intel's fabs getting on track, it is very possible for intel to win the long race. Normally it takes 4-5 years to realize one's vison, that coincides with lunar lake/ royal cove leaks thus far.

Not that I'm saying amd is doom, it's that intel's current delays are not the delays of the past.

There is always a bunch of stuff about the empire striking back, which was true previously, but isn’t actually true any more. Intel will have a tough time surpassing AMD. Even if Intel had executed much better, they would still have needed to accelerate there plans significantly, because of ARM. I read a phoronix review a while ago (Linux server and HPC) where it was AMD and ARM trading blows and Intel in third place for some benchmarks. There are still a few that Intel can win, but not many. I suspect that will be near zero after Genoa hits. Bergamo seems to be aimed more at ARM competitors than Intel.

Why is it different now? It is different because this isn’t AMD vs. Intel. This is AMD + TSMC vs. Intel. TSMC holds more than 50% of the semiconductor market. By breaking the Intel monopoly, we may actually be creating another monopoly on the fab side. Anyway, thinking that Intel will suddenly be able to dominate again is likely just not true. I am fine with that since to really break the intel monopoly requires AMD to dominate for a bit longer. A large part of Intel’s previous success was process tech superiority. That seems to no longer be the case and they do not seem to be going to take the lead again in the near future. It would be great if AMD (or Intel) can nock Nvidia down a bit also, but the cuda vendor lock-in is strong.