Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Exist50]

Considering FP workloads need the most bandwidth and Zen 4c is rumored to halve the AVX512 throughput over Zen 4 the approach you describe makes perfect sense to me.

I'd take those rumors about halving AVX512 throughput with a grain of salt. My understanding is that Zen 4 and 4c are pretty much architecturally identical.

That said, cloud tends to be int heavy, and relatively insensitive to L3 cache. I think they could get away with less die to die connectivity if necessary.

 

[jpiniero]

All AMD said is that the ISA was compatible. They didn't say anything about performance.

 

[Exist50]

All AMD said is that the ISA was compatible. They didn't say anything about performance.

They didn't, but that doesn't mean it has changed either. And frankly, AVX512 is probably the worst thing to target from a design effort standpoint. I'm not even sure it's able to be cracked, and even if its possible, that would be a substantial engineering investment for dubious gain. I'd be willing to bet we see the same behavior across Zen 4 and 4c.

 

[coercitiv]

Has anyone seen motherboard costs for the x670 chipsets?
I saw 1 article that showed the lowest (no PCIE 5.0 slot) for over 300$ USD

All I can tell is the prices will be higher than Z690 on average, and this is based on exactly one of those early listed boards, the MSI’s PRO X670-P WIFI at around $300.

When compared with the Z690-A PRO WiFi, which started out as a $220 board, the newer X670-P comes with an upgraded VRM of 14+2+1 80A stages versus 14+1+1 55A stages. The VRM cooling also loks to be improved in terms of metal mass, as does the chipset cooler. On top of that the AMD board seems to be a 7-layer PCB design, versus 6-layer on the Intel board (we need confirmation on this though). Last comes the audio part, which gets an upgrade as well.

So we have a "low cost" X670 board that is already an upgrade over the $220 board from last year, with higher BOM. On top of that we add inflation. Even if we take into consideration the "early adopter tax", I think the MSI PRO X670-P WIFI will hover around $250-270 after the price settles to a reasonable level. And as you already said, this is mostly a PCIe 4.0 board, only one M2 slot is PCIe 5.

 

[Timmah!]

These boards were model compared to the same x570 model was 220$ ish which compared to the same x670 model at 500$.
The 300$ board was the lowend x670 chipset.
Which is where my concern comes from.
That just seems outlandish.

i saw the preliminary prices for Asus boards on wccftech. I hope its not true and someone pulled those from you know where, cause cheapest 670E was like 800 EUROs, the Hero was like 1100 EUROs and Crosshair Extreme 1475 EUROs. I was like what. You could have WRX80 boards at those prices. It would explain the "E" in the naming though, extreme for extreme pricing. Cause sure as hell there is nothing "extreme" about it otherwise.

 

[Det0x]

The fastest supercomputer is operational now

https://twitter.com/x/status/1560331272806973443

 

[igor_kavinski]

Real shame for Intel. They can't save face no matter what they do.

 

[Saylick]

If the rumor is true, I can't wait to see what AMD reveals regarding their next supercomputer win, which allegedly uses Zen 4 and (my guess) also MI300.

 

[NostaSeronx]

I'm not even sure it's able to be cracked, and even if its possible, that would be a substantial engineering investment for dubious gain. I'd be willing to bet we see the same behavior across Zen 4 and 4c.

Port 0 and Port 1, every Intel AVX512 design.


AVX512 has been cracked from the start. Client so far has never seen the dedicated AVX512.

Family 19h FPU:

Purple = AVX512 (Full decode width)
Red = Low AVX512
Blue = High AVX512

Zen4c cuts FE/LSU/FPU but keeps full Integer execution.
Red&Blue execution is temporal with Zen4c: Port 0, 2, 4 are the only units available.

 

[Exist50]

Port 0 and Port 1, every Intel AVX512 design.
View attachment 66099

AVX512 has been cracked from the start. Client so far has never seen the dedicated AVX512.

Family 19h FPU:
View attachment 66102

Please don't waste my time trying to correct me if you don't even understand the terms I'm using.

 

[NostaSeronx]

Please don't waste my time trying to correct me if you don't even understand the terms I'm using.

You used the term cracked. So, far no one has explicitly stated AVX512 will not be decoded fully.

AVX512 is full-width till it hits NSQ(FPU Mapper) then it splits to Scheduler 0 and Scheduler 1... or it loads first half to Scheduler 0 then the second half to Scheduler 0.

Cracked via decode where it is a double macro-op = not occurring
Cracked via execution = Same as Intel's client cores as Port0&Port1

 

[LightningZ71]

Port 0 and Port 1, every Intel AVX512 design.
View attachment 66099

AVX512 has been cracked from the start. Client so far has never seen the dedicated AVX512.

Family 19h FPU:
View attachment 66102
Purple = AVX512 (Full decode width)
Red = Low AVX512
Blue = High AVX512

Zen4c cuts FE/LSU/FPU but keeps full Integer execution.
Red&Blue execution is temporal with Zen4c: Port 0, 2, 4 are the only units available.

Incorrect on AVX512 support (two ports on every design...)

[For Ice Lake Client, carried over to Rocket Lake, Alder Lake and we speculate Raptor Lake CLIENT]
"For the execution ports, now that Intel has moved AVX-512 into the mainstream Core design, there are a few changes. AVX-512 is now supported on Port 0 (FMA, ALU, Shift) and Port 5 (ALU, Shuffle). There is only one AVX-512 port, but also a 256-bit FMA port, so either 1x512-bit or 2x256-bit throughput is possible" - https://www.anandtech.com/show/14514/examining-intels-ice-lake-microarchitecture-and-sunny-cove/3

That's half the throughput of AVX-512 on their Xeon SKUs. This is evident on benchmarks that focus on that support. Client supports the operations, but with less throughput.

 

[Det0x]

https://twitter.com/x/status/1560292910913900548

Think i have to skip liquid metal this generation... or just use large amounts of nail polish before applying

 

[NostaSeronx]

Incorrect on AVX512 support (two ports on every design...)

[For Ice Lake Client, carried over to Rocket Lake, Alder Lake and we speculate Raptor Lake CLIENT]
"For the execution ports, now that Intel has moved AVX-512 into the mainstream Core design, there are a few changes. AVX-512 is now supported on Port 0 (FMA, ALU, Shift) and Port 5 (ALU, Shuffle). There is only one AVX-512 port, but also a 256-bit FMA port, so either 1x512-bit or 2x256-bit throughput is possible" - https://www.anandtech.com/show/14514/examining-intels-ice-lake-microarchitecture-and-sunny-cove/3

That's half the throughput of AVX-512 on their Xeon SKUs. This is evident on benchmarks that focus on that support. Client supports the operations, but with less throughput.

1. AVX512 occupies port 1 when executed in port 0.
2. AVX512 does not exist in port 5 when in client parts. Port 5 in client is AVX256, except when it is not exact behavior below;
Exact behavior in the field:
Port 0 -> Port 1 = AVX512 MUL or ADD or FMA
Port 5 -> Port 1 = AVX512 MISC (adds can go this way for speed.)
Two port execution:
Skylake-X: P0+P1
Palmcove/Cannonlake: P0+P1
Sunnycove/Icelake: P0+P1
Willowcove/Tigerlake: P0+P1
Goldencove/Alderlake: P0+P1 or P1+P5 depending on the ZMM instruction.

Port 0 and Port 1 is the behavior that AMD is using. Which is cracked execution.

AMD Zen4:
Port 0+1 = Multiply AVX512
Port 2+3 = Addition AVX512 (FMA: 0+1 bridge to 2+3; 0->2 + 1->3 simultaneously)
Port 4+5 = Misc AVX512

AMD Zen4c:
Port 0 = Half-rate Multiply AVX512
Port 2 = Half-rate Addition AVX512
Port 4 = Half-rate Misc AVX512

Neoverse N1/N2/AmpereOne (Zen4c is against this) versus Neoverse V1 (Zen4 is against this)

 

[LightningZ71]

Ahh, yes, I understand now. I misinterpreted you as indicating that all their designs had the same FMA throughput. This is different.

 

[nicalandia]

Latest Cinebench R23 ST Run on an ES sample. Cinebench can only detect 256 Threads, but this is a 384T CPU. If CBR23 could take advantage of all cores, we might be looking past 160,000 points.



ST: 1300 Points at 3.7 Ghz
MT(256T)110,000 Points at 2.15 Ghz

 

[igor_kavinski]

Latest Cinebench R23 ST Run on an ES sample. Cinebench can only detect 256 Threads, but this is a 384T CPU. If CBR23 could take advantage of all cores, we might be looking past 160,000 points.

View attachment 66110

Impressive chip. What would be the all core boost on this monster? 600W TDP, I presume?

 

[nicalandia]

Impressive chip. What would be the all core boost on this monster? 600W TDP, I presume?

It's boosting to 2.15 Ghz

 

[igor_kavinski]

It's boosting to 2.15 Ghz

So TDP should be pretty tame. Like less than 400W.

 

[nicalandia]

So TDP should be pretty tame. Like less than 400W.

Yes, I have been told that it rarely goes above 400W

 

[igor_kavinski]

Think i have to skip liquid metal this generation... or just use large amounts of nail polish before applying

Why not graphite pad?

 

[szrpx]

Yes, I have been told that it rarely goes above 400W

When you consider that roughly ~100 W or so is I/O die, that means you're looking at 280 - 300 W for cores alone. With 384 threads, you're looking at ~1.5 - 1.6 W per core, or ~0.7 - 0.8 W per thread. Ball park numbers of course.

Crazy stuff.

 

[Timmah!]

If 1300 at 3,7Ghz, then 2000 at 5,7?

 

[Panino Manino]

The fastest supercomputer is operational now

https://twitter.com/x/status/1560331272806973443

Just recently AMD was non existent on servers and suddenly now it equips the absolute fastest machines.
It's absurd how fast this happened and I can't imagine how people on Intel may feel.

 

[Vattila]

Not quite what i wanted, but my point was in principle about more focus on aesthetics and you seem to get it, as your designs looks significantly better and less busy than the original. Good work.

Thanks. Feel free to make your own — would be cool to see what you had in mind. I think there is a lot of possibilities for unexplored creativity on the IHS. Check out the Clark and Su editions in my edited post.