No the article doesn't state that. AT has a good coverage. FP unit is "streamlined" so that it's smaller and yet performs the same as old one. SO basically from execution POV they didn't expand it. Whether the rest of the core changes(which are significant) may help the FP execution ,remains to be seen. Clock frequency may suffer due to other factors (teh core is more complex now).
Having two FMA units also helps code without FMA instructions (namely by allowing two additions or two multiplications to execute each cycle).FMA also is only a fraction of all FP instructions.
It seems AMD didn't want to talk about that at this year's HC . AT article states that L3 remains unchanged(it's a part of uncore).
You expect that FMA units will be able to be fully utilized without specially compiled binaries? I find that hard to believe(look at Bulldozer to see why).Having two FMA units also helps code without FMA instructions (namely by allowing two additions or two multiplications to execute each cycle).
I doubt they will dump HT altogether but I think that current APUs don't use HT(IIRC AMD uses PCIe for Trinity and Ontario).You suppose that they start dumping hypertransport for Desktop CPUs and APUs and using the new Seamicro interconnect from 2013 onwards?
Arggg WTF AMD that's a front loader dude.
The placement of structures was hand tweaked for high clocks for Bulldozer. Post-Steamroller AMD will not hand tweak but instead automate for maximum density and power savings.I'm confused about the high-density cell libraries. I thought the problem with Bulldozer was that it used a lot of automated transistor placement, and that caused the die size and power problems. But here the article is saying that by using a (possibly different) type of automation they can get lower power consumption and smaller dies? Aren't those two exact opposites? What gives?
"Bulldozer"
Part of the Floating Point Unit. Hand-drawn for maximum speed and density in 32nm.
With High Density Library
The same blocks again, but built with a High-Density cell library to achieve 30% power and area reductions
AMD probably compressed Bulldozer by hand as best as they can. The synthetic tweaker is just better than the human tweaker.
I can accept that, but it doesn't gel with this Anandtech article...or is there something I'm missing?
So the problem with Bulldozer was apparently it was too automated.
Now AMD is saying the problem with Bulldozer was it wasn't automated enough.
???
EDIT: Oops, not that article. Some other article. Just got to find it...
EDIT2: This article. Damn, thought it was Anandtech.
Another thing is there are ENORMOUS advances in EDA tools. Seriously - if you compared the QoR of Cadence's SoC Encounter 10.1 and 10.1_USR3, you'd see a marked difference.I'm confused about the high-density cell libraries. I thought the problem with Bulldozer was that it used a lot of automated transistor placement, and that caused the die size and power problems. But here the article is saying that by using a (possibly different) type of automation they can get lower power consumption and smaller dies? Aren't those two exact opposites? What gives?
What isn't accurately captured or portrayed in those articles is that the state of the art in synthesis (automated layout) is not static, rather it is advancing at a blistering rate thanks solely due to the increasingly difficult requirements placed on fabless design houses by the foundries as the process nodes increase in complexity at every node (making hand-coded cells all the more arduous node after node).
The commentary regarding bulldozer's reliance on synthesis came from an engineer who left the company 2yrs before bulldozer came out, that is 3yrs ago. 3yrs is an eon in this industry. I'm sure his comments and experience were relevant to the state of synthesis in 2009 with 45nm, not so relevant to the state of synthesis in 2013 with 28nm.
Think of it like this...consider the game of Chess. In 1960 you would not want to bet on a computer competing against world-class chess players, the computer would stink. Same in 1970, and 1980. Computers were slow and not as good as humans.
But what happened in 1997 between Deep Blue and Kasparov? Computer won.
This is what has happened in pretty much every industry that involves engineering. Slowly but surely the software and hardware has evolved to the point where computers can run through millions of simulated models to find more optimal cases than humans could ever hope to achieve - be it with bridges, autos, skyscrapers, or integrated circuits.
It is not that the computers are smarter, its just that they are faster. So they can run through so many more test designs while filtering out the dead-ends faster than a team of humans ever could.
So the limits are not that of the CPU designers but now the limits are on the people who program the synthesis tools themselves. Very much like the limitations in programming that come at the hands of the people who create the compiler tools.
It was only a matter of time before computers would become better than human at designing CPU's. And it is a matter of budget as well. Looks like AMD is saying when you factor in the budget considerations, computers have reached that point now.
Wait wait wait... I thought THIS was universally known/admitted to be the problem with Bulldozer - the fact that they moved away from hand-tuned/drawn logic and moved to automated crap which ended up costing them in terms of power, performance AND delays.
(A quick google = first link found)
Another thing is there are ENORMOUS advances in EDA tools. Seriously - if you compared the QoR of Cadence's SoC Encounter 10.1 and 10.1_USR3, you'd see a marked difference.
<-- Just spent a bunch of time comparing QoR for Encounter 8, 10.1, 10.1 USR3 and 11.1.
Oh, and don't get me started on the f@#$*&ng binary Milkway databases that Synopsys' ICC uses. Damned things can be landmines
Going back to independent decoders for each core.
The past is the future, or something like that. Guess it invalidates the major design ideas behind bulldozer.
Be serious please. Bulldozer is faster than K8,it's around the level of first gen K10 core (65nm Barcelona). This core is ~10-15% faster than K8 in integer and 1.5-2x faster in SSE workloads. In FP stuff Bulldozer is just crushing K8 (not hard since K8 has 64bit FPU).
As far as I can tell, AMD hit the numbers that they were claiming for Piledriver. Piledriver's focus wasn't so much on performance: it was to put a clamp down the ridiculous power consumption. We don't know if that will translate to better overclocking, which is theoretically Vishera's biggest draw. At any rate, it will finally be an upgrade for AM3 users. There are some people expecting 15-20% performance improvement over Bulldozer... and I really think those expectations are ridiculous. 5-10% is my guess... like Ivy Bridge, but without the solder fiasco.People was super hyped about Pilediver too. That didnt go well...
Its a rerun every single time.