Stupid VHDL question

[smack Down]

I want to create a output port that is a two-D array. I know because VHDL is retarded you can't just create a 2D array. So I want to create a type reg64 that is an array of std_vectors( 31 downto 0 )

So the question becomes where in the file do I place the type definition.

 

[cjr22]

You can create a 2d array:

TYPE mytype IS ARRAY (NATURAL <>,NATURAL <>) OF STD_LOGIC;
SIGNAL mysignal : mytype(10 DOWNTO 0, 10 DOWNTO 0);

or

TYPE mytype IS ARRAY (31 DOWNTO 0, 1 DOWNTO 0) OF STD_LOGIC;
SIGNAL mysignal : mytype;

would work, or your plan works too. You put the type definition in a package, before the BEGIN in an architecture or process etc etc...
Wow, this is the first time I've seen a post about VHDL here. It's the only language I could be helpful in too ;-)

 

[itachi]

what cjr22 said is how u create a 2d array in vhdl.

altho.. if i'm not mistaken, the code should be:
type mytype is array (natural range <>, natural range <&gt) of std_logic;

 

[smack Down]

Originally posted by: cjr22
You can create a 2d array:

TYPE mytype IS ARRAY (NATURAL <>,NATURAL <>) OF STD_LOGIC;
SIGNAL mysignal : mytype(10 DOWNTO 0, 10 DOWNTO 0);

or

TYPE mytype IS ARRAY (31 DOWNTO 0, 1 DOWNTO 0) OF STD_LOGIC;
SIGNAL mysignal : mytype;

would work, or your plan works too. You put the type definition in a package, before the BEGIN in an architecture or process etc etc...
Wow, this is the first time I've seen a post about VHDL here. It's the only language I could be helpful in too ;-)

I know you can create them in VHDL they just are not supported by the synthisizing tool.

 

[itachi]

package typespackage is
type fake2d32 is array (natural range <&gt) of std_logic_vector (31 downto 0);
end typespackage;

use work.typespackage.all;
ENTITY someModule IS
port (
A : in std_logic_vector (31 downto 0);
B : out fake2d32 (31 downto 0);
);
END someModule;

i didn't notice this before.. but why are you trying to use a vector as the output? i can't imagine any real situations where it'd make sense to combine all the ports..