There is another way to look at this. AMD figured out a way to have a very universal chip, that could be expanded in servers with little redesign(2 CCX, 4 CCX, 8 CCX on one physical socket, etc), and then FIRST implemented the base core in desktop, to weed out any problems (Ryzen) before going with the enterprise versions. (EPYC and threadripper). Not to mention the efficiency is WAY better than the Intel desktop, HEDT or Xeon lines.
And why do you think Ryzen is ECC compatible (if the motherboard supports it). Its a server CORE !
P4 most certainly was not.
Memory channels aren't tied to CCX's, its very obvious if you look at the Zen developer guide... So what is your point exactly?Many people argued it is a server core from day 1, still i dont belive they can scale it to 8 CCX, that whould be 16 channel memory, as a modular design, it has some limits, 1 mem channel per CCX and the main memory is also partitioned per CCX. But thats not really that important for servers.
Just the fact that Ryzen supports ECC (if the motherboard supports it) proves its a server die.Intel repeatedly makes variants of the claim that EPYC is a "repurposed desktop product" (slide 47) and uses "repurposed desktop dies for server" (slide 50, 51, 54). I think this crosses the line between spin and outright falsehood. AMD clearly designed the Zeppelin die for use in servers; otherwise it would not support connecting multiple chips via the Infinity fabric. The claim that the Zeppelin dies are "glued together" (slide 50) would be derogatory but not outright false if the Zeppelin dies were not referred to as "repurposed desktop dies."
Intel does point out theoretical weaknesses of the EPYC design in slides 58 and 59, assuming you believe the numbers. (I would normally trust numbers from Intel, but the earlier slides make it hard to trust anything that comes after.) What they don't have is evidence that these theoretical weaknesses matter in actual software. The most that can be said is that it would be prudent to benchmark your software on both AMD and Intel before choosing between them.
Memory channels aren't tied to CCX's, its very obvious if you look at the Zen developer guide... So what is your point exactly?
Because they dont, unless your claiming Raven Ridge is 2 CCX's or only 1 memory channel and your also claiming that the developer guide(page 28) is lying?Why they need a memory channel per CCX then?
They don't. The memory controller is per Zeppelin die, not per CCX: https://en.wikichip.org/wiki/amd/microarchitectures/zenWhy they need a memory channel per CCX then?
Oh come on people! LOOK at this slide.. Look at how anything in red doesn't line up, font size slightly different.. EASILY you can see the red section has been added..
I'm not a fan boy or anything else. If Cyrix made a cpu that I needed I would buy it, but I ALWAYS want the truth! How many of the Zen slides turned out to be bogus?
Just provide an intel link.. That's all ..
Just wanting to clear something up here.
Yea the only text I don't see line up is text that has a different number of lines, but that's the same sized font with one line vs. two lines or two vs. three, so its how one would expect it to look. I have no idea what the other poster is going on about. Protesting a bit too much.
That kind of amateurish presentation you don't usually see from Intel.
This presentation just shows that Intel is back with their old shenanigans.
It kind of is. Much like how the whole TR and EPYC packages and memory slots are setup. A Zeppelin die has the memory channels positioned and I wouldn't be surprised if it wired specifically to each die.They don't. The memory controller is per Zeppelin die, not per CCX: https://en.wikichip.org/wiki/amd/microarchitectures/zen
There is a difference between hard-wiring (which isn't what's done here) and allocating resources in a way presumed by AMD to be most efficient. A CCX communicates with any part of the uncore only through the IF, not directly.It kind of is. Much like how the whole TR and EPYC packages and memory slots are setup. A Zeppelin die has the memory channels positioned and I wouldn't be surprised if it wired specifically to each die.
Until someone brings it to 4000k list price day one with far cheaper or more memory to boot.talk about yields and manufacturing cost is not that important in servers. $13000 SKUs!
I saw the R of Repurposed sitting on top of the dotted line and that's what bugged me about the slide. That kind of amateurish presentation you don't usually see from Intel.
Yes. That's exactly what potential server buyers will check first and foremost. The latency comparisons, amd not actual perf/W/$ regarding the worklads and specific aoftware they use. Niche market my ashtray.Now that everyone's done laughing at the glue slides, we finally got some numbers for Epyc.
https://www.servethehome.com/amd-epyc-infinity-fabric-latency-ddr4-2400-v-2666-a-snapshot/
But these are not the numbers that will usher in a new era of general purpose MCM CPUs. For comparison, ~140ns is the remote memory latency of a 112-core 4P Skylake SP system.
AMD will need to increase the core/node or improve the IF latency dramatically in the next Zen generations to break out of the niche market they've crammed themselves into.
Nah, Intel NDA/vendor only slides always look like crap. You'd think with all the billions in revenue, there would be a professional PowerPoint guy whose only job is to make all of them look nice, but no.