What exactly does that mean? Is that a good thing?
Yes, it's a good thing. It means they didn't differentiate the AGUs and the AGUs can be used for any memory op. So, it can do two loads at the same time or two stores at the same time, or one of each. There were rumors that one was load-only and the other was store-only. I think it came from a misreading of the gcc patch (since the patch creates a znver1-load and znver1-store distinction... but when you look at the definition it is znver1_agu, which is defined as znver1_agu0 | znver1_agu1, meaning either unit can do either (I missed this until yesterday and believed the rumor until then)).
AGU Specialization is used to limit how many connections you need to make to an AGU and to reduce the complexity of handling multiple AGUs and generated addresses at once elsewhere in the design. Intel's Core chips (up until Sandy Bridge) used this design. AMD, however, has had full AGUs since the Phenom era, IIRC (a requirement of the clustered design), which was even considered one of their weak points against the Core architecture by some (entirely as a side-effect of the cluster design (1AGU + 1ALU attached to a queue, which complicated scheduling and meant stalls were more likely)).
Sandy Bridge has two full AGUs and they discovered the greater benefit came from just the extra store AGU capability (the extra load was still helpful, but really only for SMT). Haswell has those plus an addiitional store-only AGU. It gained them relatively little, which illustrates just how well two individually addressable fully functional AGUs can operate.
If we compare Zen to Sandy Bridge, we learn a few things that are interesting.
Sandy Bridge has 3 ALUs and 2 AGUs.
Zen has 4 ALUs and 2 AGUs.
Sandy Bridge shares its 3 ALU pipes with floating point instructions.
Zen has 4 dedicated floating point pipes.
There are certain cases where this pipeline dedication will be a meaningful benefit for Zen, such as when one thread is integer heavy and the other is floating point heavy (quite common, actually) while using SMT, or when on thread uses a great deal of each (which is fairly common in unoptimized complex loops).