It means that Samsung LPE is competitive with TSMC s 16FF+...
I like to think that my posts are fairly analytical, but obviously as a judge of my own posts I am not exactly impartial
The bottom line is that the expectations around Zen and Zen-based products seem to be inflating with each and every day.
All we know for sure about Zen is that AMD has said that perf/clock goes up by around 40% relative to Excavator and that AMD expects Zen to make the company much more competitive than it has been over the last several years in high performance processors.
Anything beyond that is basically (informed?) speculation.
The original point that I was trying to make in the text that you quoted is that high IPC/high frequency x86 CPUs are really, really hard to design and build. The reason we see 5-10% IPC improvement per generation from Intel is because wringing out those gains is actually super tough and R&D intensive, especially since Intel needs to make these IPC boosts while keeping frequencies high and keeping power efficiency in check.
If it is proving tough for Intel to scale these new performance heights, I have to maintain a fairly high degree of skepticism about AMD's ability to deliver a design in basically one shot that effectively erases the perf/clock gap that has long existed between Intel's and AMD's top designs while at the same time delivering high clocks, and great power efficiency.
We will see if AMD ultimately delivers but from every bit of information available to me in the public domain, I can't exactly be enthusiastic that Zen will be what some of these posters hope. That's all.
If you would only ported Excavator to 14nm LPP, you would get the same performance (lets say A10-7870K) at ~60% lower power and at ~half the die area.
Just think about it.
Then why did Apple go with TSMC 16FF+ for the entirety of the upcoming A10 orders?
I don't think it's that simple. Take Intel's 14nm for example. At very high frequencies (i.e. 4GHz+) Skylake is barely any more efficient than Haswell is (might even be less efficient?), but at lower frequencies (i.e. the ones we see in Ultrabooks and even "H" series laptop processors) the efficiency story favors 14nm over 22nm quite nicely.
It s possible that LPE is slightly below TSMC s 16FF+, and/or because of manufacturing capacity as Samsung use it for themselves, besides it s better for Apple to wait for the LPP as it will bring 10% better perfs or 20% lower power, that s not negligible given that Apple segments require above average perfs..
Shhh, they are ready to call you a fanboy now that they know you don't buy the hype.
The only reason I question that A9 is built on LPE and not LPP to be honest is because when I have asked around, I have been told that A9 is an LPP design not LPE, but the confidence level around these answers was good but not 100%.
That's why I'd appreciate any "hard" evidence one way or another because I am legitimately curious.
Right. Sorry for attacking you numerous times.
I'm thinking that because various sources indicate the same process used to make the Exynos 7420 which used LPE and it would have made sense that the A9 did as well as I don't think it would be feasible for Samsung to produce LPE chips for the Exynos AND be manufacturing LPP chips. Do you have a link for your sources?
The only reason I question that A9 is built on LPE and not LPP to be honest is because when I have asked around, I have been told that A9 is an LPP design not LPE, but the confidence level around these answers was good but not 100%.
That's why I'd appreciate any "hard" evidence one way or another because I am legitimately curious.
You need some data to support a "most likely". With the available information from the GCC patch and no need to have clock frequencies (IPC!), it's possible to show multiple scenarios, where more than 40% could be achieved, even assuming, that they keep the XV bottlenecks in the cache subsystem.Why should we believe that they have reached 40% higher IPC than Excavator?
We don't even know what they mean by that.
Most likely, the 40% should be preceded by "up to".
It means that Samsung LPE is competitive with TSMC s 16FF+...
Love your blog posts btw.You need some data to support a "most likely". With the available information from the GCC patch and no need to have clock frequencies (IPC!), it's possible to show multiple scenarios, where more than 40% could be achieved, even assuming, that they keep the XV bottlenecks in the cache subsystem.
From my POV they'd need to add pause cycles to keep a absolute max. 40% IPC gain.
So I opt for a simulated average value with the remaining question: what's the application mix?
100% more integer exe ressources than an EXV core, 150% more FP exe ressources than a whole module...
The 14nm LVT, the one whose perf/Watt were published, would double the perf/watt of a chip like Kaveri, and there s a faster sLVT enhancement..
I have no doubt that you you ll be deeply disappointed...
Hey, where have you been? I thought you only got 30 days, but it's been over two months.
That seems to be true for the normal phone use case where the chip is mostly idle, but the iPhones with the Samsung chip have substantially lower battery life than the TSMC ones when under a heavy load (geekbench). I hope LPP is a lot better than LPE, because AMD will have a hard time competing on power use if that's not the case.
He became a fanboy.
Please read the rules, calling someone a fanboy is not allowed in the technical forums.
You need some data to support a "most likely". With the available information from the GCC patch and no need to have clock frequencies (IPC!), it's possible to show multiple scenarios, where more than 40% could be achieved, even assuming, that they keep the XV bottlenecks in the cache subsystem.
From my POV they'd need to add pause cycles to keep a absolute max. 40% IPC gain.
So I opt for a simulated average value with the remaining question: what's the application mix?
I like to think that my posts are fairly analytical, but obviously as a judge of my own posts I am not exactly impartial
The bottom line is that the expectations around Zen and Zen-based products seem to be inflating with each and every day.
All we know for sure about Zen is that AMD has said that perf/clock goes up by around 40% relative to Excavator and that AMD expects Zen to make the company much more competitive than it has been over the last several years in high performance processors.
Anything beyond that is basically (informed?) speculation.
The original point that I was trying to make in the text that you quoted is that high IPC/high frequency x86 CPUs are really, really hard to design and build. The reason we see 5-10% IPC improvement per generation from Intel is because wringing out those gains is actually super tough and R&D intensive, especially since Intel needs to make these IPC boosts while keeping frequencies high and keeping power efficiency in check.
If it is proving tough for Intel to scale these new performance heights, I have to maintain a fairly high degree of skepticism about AMD's ability to deliver a design in basically one shot that effectively erases the perf/clock gap that has long existed between Intel's and AMD's top designs while at the same time delivering high clocks, and great power efficiency.
We will see if AMD ultimately delivers but from every bit of information available to me in the public domain, I can't exactly be enthusiastic that Zen will be what some of these posters hope. That's all.
More numbers...
GLOBAL FOUNDRIES FINFETS VS 28NMs
GF PROCESS 28 SLP 28 HPP 14 LPP
Using the recent past performance of a company to form expectations of what type of product they will release makes one a "shill"?
How do you figure?
Which is magical thinking? Expecting a company's to perform similarly to how they have been for the last 6 years or so, or expecting some massive improvement despite fewer resources.
Intel has you convinced that it is difficult for them to give you more performance, that's just what they want you to think.
If Intel wanted to give you more, they'd give you more. The only factor is achievable profit margin. Intel could absolutely give bigger performance jumps, but it would be unusual for them do so.
Since Penryn, they really haven't been that inconsistent:
Something to pay attention to here, as well, is that Excavator is pretty much dead even with Penryn for IPC. Add 40% add you land square on Haswell.
I'm really surprised anyone thinks Zen will reach Skylake at all.
Thinking it might be the next Bulldozer is at least somewhat reasonable (though the fact that AMD stumbled that bad... once... means nothing... I seem to remember Intel doing something quite similar ^_^:whiste)).
So would you care to explain how giving less performance leads to bigger profits? Seems to me more performance gains would lead to more sales (new sales and upgrades), thus more profits. Do you really think Intel is purposely holding back performance, especially with the increasing competition from ARM and Mobile?
It is a simple fact that the easy gains have been made long ago and every incremental gain becomes increasingly difficult, especially when trying to do it in a power constrained envelope.
You need some data to support a "most likely". With the available information from the GCC patch and no need to have clock frequencies (IPC!), it's possible to show multiple scenarios, where more than 40% could be achieved, even assuming, that they keep the XV bottlenecks in the cache subsystem.
From my POV they'd need to add pause cycles to keep a absolute max. 40% IPC gain.
So I opt for a simulated average value with the remaining question: what's the application mix?