I don't think that AMD will price its 8 core Zen particularly cheaply and there is a very simple reason why.
Are you saying Intel can never recover from their Pentium 4 debacle
AMD stumbles one time and you automatically assume they will stumble again when they have done so much that clearly shows they are on the right track? They even brought in a great deal of specialized talent (more than just Jim Keller, he's just the biggest name), but some who had FinFet experience.
With what we know about Zen (which is more than many seem to realize), it should be quite an interesting CPU. The FPU is what we don't really know it will perform, though I've done some work towards estimating that:
http://looncraz.net/ZenAssignments.html
Intel has you convinced that it is difficult for them to give you more performance, that's just what they want you to think.
If Intel wanted to give you more, they'd give you more. The only factor is achievable profit margin. Intel could absolutely give bigger performance jumps, but it would be unusual for them do so.
Between the launch of the Pentium 4 in the year 2000 and the launch of Core 2 Duo in 2006, Intel's R&D spending rose sharply from just north of $3 billion to nearly $6 billion, meaning that Intel actively upped its investments substantially between the Pentium 4 "failure" and Core 2 "salvation".
AMD has shed talent and its R&D budget now sits below $1b/yr in today's dollars, and this includes what should be a fairly major GPU effort. Just FYI.
How much does it cost to design a CPU core......... R&D as a total value is irrelevant without understand how it is being spent (you dont).
So would you care to explain how giving less performance leads to bigger profits? Seems to me more performance gains would lead to more sales (new sales and upgrades), thus more profits. Do you really think Intel is purposely holding back performance, especially with the increasing competition from ARM and Mobile?
It is a simple fact that the easy gains have been made long ago and every incremental gain becomes increasingly difficult, especially when trying to do it in a power constrained envelope.
You're right, my bad, I have absolutely no clue what I'm talking about. Things are going just swimmingly for AMD and life is going to be just smooth sailin' for them from now on. Yep.
Sure. Intel doesn't have to worry about performance to drive sales, they have no competition. The user upgrade market is quite small compared to the OEM market as well, so they can make more money by release only small upgrades and charging those who make the jump each time (or many of the times) out the yang.
The real money is in servers. There, Intel is in the same situation. They have no competition, so they only advance as much as they must to keep sales up and margins high.
While x86 gains are certainly not extremely simple, if you look at the changes Intel has made to the Core design to get us what we have today it is quite clear that they have only been doing what it takes to provide a small boost that will keep people interested and give the OEMs a more expensive CPU to purchase.
Every change is incremental and simple (for the most part). These are things we said Intel could do when Core 2s were out and about to increase performance (full AGUs, another ALU and FPU port, more scheduler slots, improved branch prediction, etc.) together with a few things that are more unique (reduced misprediction penalties).
Almost everything Intel has done has been to give the illusion of struggling to create more performance. They keep a GPU on these dies that will often go completely unused in higher end systems... they could EASILY take that off and use that die space to provide more performance. Either with two more cores or with wider cores.
The biggest hurdle to overcome is the microcode itself. When you add an ALU you have to know what you will have execute with it, same with an extra FPU pipe.
Want to know how to make it wildly faster? Easy:
8xALU/FPU pipes, 4x AGUs, 1x Store AGU, 1x Store Data, double the caches, double the instruction fetch, double the register pool, etc. Assign four logical cores to this core and use a single unified scheduler.
Now, each thread can potentially access 2x MUL, 2x DIV, 8x ADD, 8xLEA, 4x LOAD, 5xSTORE, 8x fop, etc... all at once.
You throw all of the instructions into the same cache, without any regard for which thread owns what, and you pull the instructions. When an instruction goes through decoding the register is chosen in the pool based on the thread to which the instruction belongs, and the data is loaded, and the instruction continues like nothing else is different.
This is completely doable, and would easily fit in the die space (it would actually be a bit smaller than two cores, but should perform just as well). With Intel's economies of scale this would probably even be affordable for those who *really* need high IPC.
Of course, this will NOT double IPC, as there's always a point in the code where you start working a bit too far out of the context and there are legacy concerns, but this is worth a good 50% single threaded boost.
You would then have Celerons and Pentiums with one super-fast core and two or more threads.
Boy, you sure do make it sound easy to build an "Intel-killer" chip to take advantage of the fact that Intel is just lazing about dribbling out performance increases. Maybe AMD should hire you to run their CPU division?
Please note that he suggested those modifications. No one is necessarily saying that it would be easy to implement those changes but for a company like Intel who you point out continuously as having a large Research and Development budget, they *should* be able to. You also mention how the engineers at AMD aren't as good as Intel's either. Why can't the combination of pure genius and immense amount of money come up with an extremely powerful CPU? One change in particular which was relating to removing the iGPU in the 6500K or the 6600K, why doesn't intel do that? Why not free up transistors for the CPU?
This so much. The unified socket will be glorious. Pick up a decent mobo and you'll have great upgrade paths available. Way better than paying more for an X99 mobo or one that is designed for OCing or one that has these extra features that the other ones don't have because of different chipsets etc...This immediately makes Zen better for me if it matches Haswell.
That, and Zen+ will most likely use the AM4 socket as well which means an even bigger upgrade path.
<br />How much does it cost to design a CPU core......... R&D as a total value is irrelevant without understand how it is being spent (you dont). <br />
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AMD isn't going to do to anything revolutionary here, its going to be evolutionary, and many parts of both bulldozer and cat cores are in really good shape to use as a base. For all bulldozers suckieness it actually did lots of good things they just all ended up horribly bottlenecked <img src="images/smilies/familiar/sneaky.gif" border="0" alt="" title="Sneaky" smilieid="40" class="inlineimg" />....<br />
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op/loop cache, decode, PRF, prefetch,predictors, load and store, DVFS. AMD already have a good handle on TSV, MCM as well. So i bet we are going to see evolutions of these area's. We know we are seeing changes in both INT and FP execution units. But it looks like the caching system will be completely new.<br />
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So now how much R&D $ does it cost of 4 years to bring that kind of product to market? how are you coming to that figure? Without that your point is irrelevant.
Thanks for posting the numbers ;-)
Just goes to show what I've had to tell so many people, there's really no reason why Zen shouldn't be able to clock well on 14nm LPP - beyond AMD's lack of experience with it and the new IP involved (if anything's going to slow down the clock speeds, I think it'll be the caches).
good work,
1. you moved the goal posts
2. you didn't address a single point
3. you then said i said something that i didn't.
congrats on the trifecta....... :\
OK, so confirmed it 100%: A9 is LPP not LPE.
LOL.
You should mail a few sites to tell them that they are wrong and that you know better...
What's so funny? Unlike most of the sites that have been blindly parroted that A9 is built on 14nm LPE, I went and did the work required to learn what process A9 is actually built on. This information has been verified with multiple industry sources, so I have confidence in it. You can "LOL" all you want though.
Verified and no link posted...
Because Hardware.fr dont have their own sources, neither does THG....
Looncraz, it's not that easy to add units, reduce misprediction penalties, and so on. Scheduler complexity and power consumption would quickly go up. Pipelines aren't changed that easily etc. Design tools were less advanced in the past.
Soon or later you'll be able to actually play with your ideas.
No doubt, but in this day of synthesized designs and capable tools there's really not much excuse. In fact, for the last decade it has been rather simple to add new logical units into a CPU and have the physical design finish itself.
...
They could go as far as to power and clock gate each execution unit so that they are only sucking power when in use.
I am not so sure about that. The Performance rating was outright disasterous. It took K6 to actually compete with Pentiums.
The clock speed of chips is limited by the longest path, both in transistors that need to switch and wire distance that needs to be crossed, that has to be traversable in a single clock cycle. This longest path is almost invariably found in the forwarding network that shuffles results from one execution unit to another. Adding more execution units is very easy, but it also directly reduces the maximum clock speed of your chip.