[Techpowerup] AMD "Zen" CPU Prototypes Tested, "Meet all Expectations"

[itsmydamnation]

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Hey itsmydammnation, do you think that the biggest part of Zen IPC increase come from beefing up the excution engine per core(like adding two ALUs and doubling the per core FPU)?

yes and no....lol

The idea of race to sleep/stall is an important one so more INT ALU is a good thing and in high ILP scenarios AMD probably was/is at a large disadvantage to intel right now.

Given that AMD moved some instructions from ALU to AGU from bulldozer->piledriver is a good indication that con cores are ALU limited. The idea that 30-50% of x86 instructions contain address gen(execution + address gen) yet bulldozer is 2ALU:2AGU also points that way.

FP being 4 wide will be interesting, most "normal" FP code (written by code monkey) is float, double etc not SIMD, So having 4 low latency execution units should be good for that race to stall idea. it is more complex then that as x86 uses x87 for these and x64 uses SSE so we will have to wait and see how much focus amd give x86/x87.

On the flip side i guess i hope AMD can reduce misspredict and the misspredict penalty which even from piledriver to excavator are better ( on the assumption a uop cache hit reduces pipeline length) then bulldozer. Given Zen is targeting a lower clock rate the pipeline length will be interesting to see.

But i think the cache system will be the really critical thing we don't know anything about it yet. latency, inclusive/exclusive ( something horrible in the middle like bulldozer ) is it a ring, a mesh, some sort of "fabric" how does it work across silicon imposer etc.

as a layman i think what we know about Zen (mainly from the compiler patch) looks good, i think we will see stuff from both the cat and con cores used as the base of which Zen is built on but i really think the uncore will be the linchpin. get that right and all is good, get that wrong :'( ........

 

[ShintaiDK]

You did exactly what I said you would and confused IPC and outright performance. The PR system was a dumb move all around, but clock for clock the K5 was really quite good in terms of integer performance. Floating point...that would have to wait (K6 2 if you count SIMD, but K7 for x87 performance). The issue with the K5 was just that they could only get to about 116mhz if memory serves correct. Even then, outside of gaming it held up well enough for where it was priced. Not a great chip by any means though.

Look again. The top bin K5 at 133Mhz (PR200) loses to a 120Mhz Pentium.

Also take a look here. I was right about the K5 PR 166 being ~116 mhz. Anytime the FPU was hit, it performed similar to the Pentium clock for clock but on integer loads, the PR rating was fairly justified.

http://thandor.net/object/314

You should check your link more carefully. The K5 gets beaten so badly by low clocked Pentiums in 4 of the 6 tests. The K5 was simply awful.

 

[nismotigerwvu]

Look again. The top bin K5 at 133Mhz (PR200) loses to a 120Mhz Pentium.



You should check your link more carefully. The K5 gets beaten so badly by low clocked Pentiums in 4 of the 6 tests. The K5 was simply awful.

Did you even read any of that? There are no benchmarks of the 133mhz chip. That was the K5 PR200. Go ahead, crtl-f and pop that in there on that page. You won't find it. Back on point, I was talking about the PR 166 (notice how it says Clock frequency 116mhz at the top?). Let's go through the list in it's entirety there for you.

Dhrystone
The PR166 performs between a 150 and 166 mhz Pentium and is comfortably ahead of the 120mhz Pentium.

Doom
The PR166 is within 2% of a Pentium 166 and is about 13% ahead of the Pentium 120.

Dosbench
Runaway victory for the Pentiums here

MDK
PR166 lags the Pentium 120 by about 20% here and isn't anywhere close to the 166

Quake
Pr166 again lags behind the Pentium 120 by a bit less than 20% and isn't anywhere close to the 166.

Whetstone
PR166 scores about half of what the Pentium 120 can produce.

The results line up with what I said. In integer based workloads (so Dhrystone and Doom) the PR rating is fairly justified. When floating point comes into play (Whetstone, MDK, Quake) the results get ugly. Depending on how how heavy the bias for FP is in the code, you'll see the K5 either drift a bit behind clock for clock or get absolutely hammered when it is pure FP calculations. However, in 1996 there really weren't that many FP heavy applications outside of CAD and 3D games (Quake would have been just released at this point). Business users or nongamers would have seen their K5 performing right about where the PR rating pegged it. I'm not arguing it was a great chip, I'm just saying on integer workloads it had much greater IPC than the Pentium, which is what the conversation was at when I first made the comment anyways.

 

[mikk]

LOL.

You should mail a few sites to tell them that they are wrong and that you know better...

Anyway this has nothing to do with Zen other than some people hoping that the process is no good.

Confirmed by Qualcomm.


http://www.computerbase.de/2015-11/...m-bestaetigt-14-nm-lpp-fertigung-bei-samsung/

 

[AtenRa]

Samsung production of the 14nm LPE Exynos 7420 SOC started early 2015 and the Galaxy S6 was released on June 2015.
Apples iPhone 6s and 6s Plus were just released on November 2015 and they use the 14nm LPP ???

Not likely. It would mean that Samsung 14nm LPP was ready for production by Q1 2015. That is not possible because that is when the 14nm LPE started.

 

[TechGod123]

Samsung production of the 14nm LPE Exynos 7420 SOC started early 2015 and the Galaxy S6 was released on June 2015.
Apples iPhone 6s and 6s Plus were just released on November 2015 and they use the 14nm LPP ???

Not likely. It would mean that Samsung 14nm LPP was ready for production by Q1 2015. That is not possible because that is when the 14nm LPE started.

I tried to say that to the other guy...

 

[Arachnotronic]

Samsung production of the 14nm LPE Exynos 7420 SOC started early 2015 and the Galaxy S6 was released on June 2015.
Apples iPhone 6s and 6s Plus were just released on November 2015 and they use the 14nm LPP ???

Not likely. It would mean that Samsung 14nm LPP was ready for production by Q1 2015. That is not possible because that is when the 14nm LPE started.

I have literally, not figuratively, spoken with multiple independent sources within the industry who have confirmed to me that the A9 is the very first product to go into production on 14LPP.

I know some of the TSMC haters/Samsung boosters want so desperately for 14LPE to be equivalent to 16FF+, but this is the reality.

 

[ShintaiDK]

Did you even read any of that? There are no benchmarks of the 133mhz chip. That was the K5 PR200.

The benchmark I linked had a K5 133Mhz (PR200).

 

[Arachnotronic]

Samsung production of the 14nm LPE Exynos 7420 SOC started early 2015 and the Galaxy S6 was released on June 2015.
Apples iPhone 6s and 6s Plus were just released on November 2015 and they use the 14nm LPP ???

Not likely. It would mean that Samsung 14nm LPP was ready for production by Q1 2015. That is not possible because that is when the 14nm LPE started.

BTW Exyos 7420 began production around October 2014 and the handset launched in April. A9 began ramping later.

 

[ShintaiDK]

Ye, A9 is LPP.

 

[Abwx]

Confirmed by Qualcomm.


http://www.computerbase.de/2015-11/...m-bestaetigt-14-nm-lpp-fertigung-bei-samsung/

Qualcomm is not Apple...

And for the 100th time there s 4 flavour of LPP...

Anyway it s funny that the Intel brigade is deseperately banking on GF screwing their RM, look that they understood that the uarch let no doubt about the targeted perfs...

I have literally, not figuratively, spoken with multiple independent sources within the industry who have confirmed to me that the A9 is the very first product to go into production on 14LPP.

I know some of the TSMC haters/Samsung boosters want so desperately for 14LPE to be equivalent to 16FF+, but this is the reality.

People who write LPP without mention of the flavour dont know what they are talking about.

The RVT has been showcased at 1.8 and the LVT at 2.4, the sLVT should be optimal over 3GHZ while the HVT is limited to 1.5GHz.

Wich one of thoses process are used in phones...??.

You would be hard pressed to tell wich one and why this one, at this point one need something else than marketing discourse to susain a point.

Ye, A9 is LPP.

Only the Intel brigade of this site say so, at odd with all sites..

And as said above LPP in isolation mean nothing.

 

[Abwx]

I have literally, not figuratively, spoken with multiple independent sources within the industry who have confirmed to me that the A9 is the very first product to go into production on 14LPP.

Not the first product that went into production on 14LPP.??.

Curious that they are implying that this still not the case...

 

[Arachnotronic]

Not the first product that went into production on 14LPP.??.

Curious that they are implying that this still not the case...

No, the sources are not implying that at all.

A9 is built on LPP. And honestly if you think about it it makes sense. Why would Apple use an inferior process and allow Qualcomm, etc. to get an advantage over the A9 by using LPE?

 

[Abwx]

A9 is built on LPP. And honestly if you think about it it makes sense. Why would Apple use an inferior process and allow Qualcomm, etc. to get an advantage over the A9 by using LPE?

To be first to market for months, and they can use LPP when it s available as well hence negating any advantage QC could get.

Now that this question was answered can this thread be left on point, i dont see what Apple has to do with Zen.

 

[AtenRa]

Samsung announced they begun mass production on the 14nm process in February 2015.

http://www.businesswire.com/news/ho...roduction-Industry’s-14nm-FinFET#.VOYa6yvF83x

February 15, 2015 09:00 PM Eastern Standard Time
SEOUL, South Korea--(BUSINESS WIRE)--Samsung Electronics Co., Ltd., a world leader in advanced semiconductor solutions, announced that it has begun mass production of industry’s first mobile application processor using the advanced 14-nanometer (nm) FinFET process technology.

Either both 14nm LPE AND LPP were ready for mass production in H1 2015 or every 14nm product in 2015 is made with the LPE. And i highly doubt Samsung had the 14nm LPP ready for mas production in H1 2015. If they had they would use it for their own Exunos 7240, instead they used the 14nm LPE for that SoC.

Also, if 14nm LPP was ready in H1 2015, that means that Samsung had 14nm LPP in production only one year after Intel's 14nm FF (Q1 2014).

 

[Arachnotronic]

Now that this question was answered can this thread be left on point, i dont see what Apple has to do with Zen.

Right, I don't either. We should stop talking about Apple

 

[Abwx]

GF LPP is relevant to the discussion, though, what interest us is how it performs compared to the 28nm HPP, although the LVT variant is unlikely to be used by AMD for anything else than GPU it s still a good indication of what we can expect from the sLVT.

Here the summary of the perfs with either the 14nm LPP LVT or the 28nm HPP, test is done with a dual core ARM chip.


GLOBAL FOUNDRIES FINFETS VS 28NMs

28 HPP
Test conditions is 0.85V in a -40 to 125°C range.
Max frequency is measured at 0.85V x 0.9 = 0.765V wich is a 10% voltage margin.
Power is measured at 10% excess voltage, that is at 0.985V.

Fmax 1.17 GHz
Dynamic power 210mW
Leakage 119mW



14nm LPP LVT
Test conditions is 0.8V in a -40 to 125°C range.
Max frequency is measured at 0.8V x 0.9 = 0.72V wich is a 10% voltage margin.
Power is measured at 10% excess voltage, that is at 0.88V.

Fmax 2.41 GHz
Dynamic power 310mW
Leakage 18.6mW

This is data that can be used for a discussion, references to products from firm A or B are for the ones who do not understand the meaning of thoses numbers let alone extract subjacent informations..

FTR with the dynamic power and frequency we can easily deduce the parasistic capacitance improvement, and from here combining with the voltage we can also deduce the improvement in transistors conductances.

 

[NostaSeronx]

You didn't hear it from me. High potential that Zen/K12/Cheetah/Tiger/Artic Islands being cancelled. Some high placed people getting the boot again.

Subtle hints that Boston has fixed Bulldozer AsyMT using ScSMT and CSMT techniques. There is also a new graphic core in town at Boston as well. Might be Supervector and CISC, ~2 GHz on whatever node that is planned. It is said to be better than Xeon Phi and fully compliant with HSA.

 

[Arachnotronic]

You didn't hear it from me. High potential that Zen/K12/Cheetah/Tiger/Artic Islands being cancelled. Some high placed people getting the boot again.

Subtle hints that Boston has fixed Bulldozer AsyMT using ScSMT and CSMT techniques. There is also a new graphic core in town at Boston as well. Might be Supervector and CISC, ~2 GHz on whatever node that is planned.

Lol, no.

 

[nismotigerwvu]

The benchmark I linked had a K5 133Mhz (PR200).

From the way you worded your response I thought you were referring to the link I posted. That and with all those JEPG artifacts I sort of scrolled right past without really absorbing much. That's the bummer on this topic though, you're reaching back into the early~ish days of the internet and it isn't exactly easy to find many reliable sources on this parts 20 years later. It's also interesting to see the drastic swings in results from the various synthetic benchmarks as well, where Sissoft's suite showed a similiar FP result to Whetstone, the integer score was nothing near why Dhrystone showed. Then again, no one really trusted synthetics anyways as they were pretty far removed from actual code. Searching around a little more I saw that a 15 year old Anand thought a lot of the K5.

http://www.anandtech.com/show/40

Oh and that 133mhz PR200 chip basically didn't exist btw. Apparently it only had a tiny run and was nearly impossible to find in anything, anywhere. Things used to be so much more interesting. Could you imagine the response if something like the 1ghz Pentium III case happened today?

 

[CHADBOGA]

To be first to market for months, and they can use LPP when it s available as well hence negating any advantage QC could get.

Now that this question was answered can this thread be left on point, i dont see what Apple has to do with Zen.

Abwx,
I see you were utterly defeated on Semi-Accurate by the Internet STRONGMAN, Juanrga. :biggrin:

 

[Bryf50]

You didn't hear it from me. High potential that Zen/K12/Cheetah/Tiger/Artic Islands being cancelled. Some high placed people getting the boot again.

Subtle hints that Boston has fixed Bulldozer AsyMT using ScSMT and CSMT techniques. There is also a new graphic core in town at Boston as well. Might be Supervector and CISC, ~2 GHz on whatever node that is planned. It said to be better than Xeon Phi and fully compliant with HSA.

They day AMD cancels literally all of their current projects is the day AMD closes their doors. We're not quite there yet.

 

[Azuma Hazuki]

Nosta, where are you getting all this information from? You sound like you really know your stuff, showing a technical grasp I've only ever seen from Looncraz before (and both of you have disturbing cat avatars...weird). But this is so far beyond the pale.

 

[Phynaz]

You didn't hear it from me. High potential that Zen/K12/Cheetah/Tiger/Artic Islands being cancelled. Some high placed people getting the boot again.

Subtle hints that Boston has fixed Bulldozer AsyMT using ScSMT and CSMT techniques. There is also a new graphic core in town at Boston as well. Might be Supervector and CISC, ~2 GHz on whatever node that is planned. It is said to be better than Xeon Phi and fully compliant with HSA.

Why do you make this stuff up?

 

[PPB]

You didn't hear it from me. High potential that Zen/K12/Cheetah/Tiger/Artic Islands being cancelled. Some high placed people getting the boot again.

Subtle hints that Boston has fixed Bulldozer AsyMT using ScSMT and CSMT techniques. There is also a new graphic core in town at Boston as well. Might be Supervector and CISC, ~2 GHz on whatever node that is planned. It is said to be better than Xeon Phi and fully compliant with HSA.

Would be more beliavable if you said their fixed their construction cores finding better cache implementations. But yeah 2/10 gotta keep trying.