So Intel has 8C/16T + iGPU, 4C/8T + iGPU, 2C/4T + iGPU (?) for 10nm.
What does AMD launch for Zen APU?
4C/8T + "big" iGPU?
2C/4T + "medium" iGPU?
(Or maybe instead of that 2C/4T + medium iGPU they instead launch a 4C/8T with "small iGPU" and bin as 3C/6T for 5W? Or maybe worst case scenario take the 2 best of 4 cores for 5W?)
I don't think anybody really knows. All the APU products are coming under the monickers of Raven Ridge and Basilisk. I expect the low-power solutions for mobile to be Basilisk. Those are probably going to be 2c/4t implementations. There is still that massive 200-300W behemoth APU, for an unknown socket (hopefully AM4 but you never know) with totally unknown specs. But if you look at the power requirements for Fury Nano, for example, you can see a massive GCN 1.2 GPU + HBM fitting inside a sub-200W envelope on a 28nm process. On 14nm LPP, that entire GPU could sit alongside a 95W 8c/16t and fit inside a 300W power envelope. Probably.
What fits in-between is anyone's guess, and the roadmaps are not clear about that.
For the sake of the argument, what is the minimum increase a Zen core must gain in IPC in order to reach the same throughput as XV? (considering SMT brings smaller benefits than CMT)
That's an excellent question, which leads us to question how AMD has chosen to use the acronym "IPC".
The definition favored by those who focus on performance from single-threaded software shows us a very different picture than if we focus on overall performance, that is, throughput.
We know that Zen is being focused on the server market. AMD is likely not all that concerned with how Zen is going to perform when running software that uses n/2 threads, where n happens to be the total thread capacity of any given Zen processor. So, they are more interested in massively-parallel workloads, such as those that can load up 16+ threads, rather than those workloads that struggle to utilize 8 cores or less.
It would genuinely surprise me if their commentary regarding IPC is somehow related to how fast Zen will be when handling a single thread per core vs. XV handling a single thread per module - that is a comparison that has almost no meaning in Zen's target market. Also, from the technical details we have received about Zen, it certainly appears as though Zen has at least as many (if not more) resources available per core versus an XV module. Zen's performance characteristics may be lopsided in favor of the first thread per core thanks to an SMT implementation that may only add 30% total throughput per core, but overall, I would expect a Zen core to outperform an XV module when handling the same two threads.
To reiterate what I've said before, if each Zen core + SMT can not put up 40% better performance than an XV module when handling two threads from some average workload, then AMD has spread misinformation. They should be more clear about exactly what they mean by IPC, especially in a contentious comparison involving a relatively-exotic design like XV.
"We expect across a wide variety of workloads for Barcelona to outperform Clovertown by 40 percent"
"We came to the conclusion that, given the capabilities and performance with the monolithic design, it was clearly the right answer"
-AMD
http://www.cnet.com/news/amd-go-to-barcelona-over-clovertown/
There is nothing technical about that argument. It's a simple matter of trust.
Either you trust AMD to deliver on their promises, or you don't. If you don't, that's fine, but again, that is not based on any technical information we have received to date about Zen or it's 14nm LPP process.