If you want to count integrated as on-die, it's essentially a tie. The E-350 came out a few days before Sandy Bridge launched in January 2011, so I guess technically AMD launched on-die graphics first. If you count Zecate as a real CPU.
Well, if we're talking x86 products, the first wasn't AMD or Intel, it was actually Cyrix back with the MediaGX in 1997.
But yeah, Intel had the first iGPU with Clarkdale, albeit in a very clumsy, hack-job form; Sandy Bridge was the first one to have it properly integrated.
This is amd in a nutshell.APU is a little different from an iGPU. I don't think Intel's ever really pushed hard on GPU acceleration using their on-die GPU. AMD's public vision was always that there would be great integration between the CPU and GPU. It's a great idea, but thus far pretty much everything treats it as a CPU with a GPU stuck on it. Back almost 5 years ago at the Llano launch big things were planned for HSA
We're still at integration, really. Same place we were when Llano launched.
Well, if we're talking x86 products, the first wasn't AMD or Intel, it was actually Cyrix back with the MediaGX in 1997.
But yeah, Intel had the first iGPU with Clarkdale, albeit in a very clumsy, hack-job form; Sandy Bridge was the first one to have it properly integrated.
In what way? Intel copied the concept BTW.
Which AMD? Today's AMD wouldn't be able to carry on these projects, but the AMD of 2010 would. The company spent a lot more on R&D and had a much larger work force than today. It wasn't lack of resources that hindered AMD in the first place, but the limitations of a failed concept (CMT) coupled with a failed architecture (Bulldozer) and failed product conception (APU).
Had AMD more resources to spare and if they decided to spare on the CMT line up, the result would be just a deeper hole.
Well, if we're talking x86 products, the first wasn't AMD or Intel, it was actually Cyrix back with the MediaGX in 1997.
Yusuke Ohara on ascii.jp estimated 3GHz for Zen (8 core I think). Without turbo and avg. 40% IPC increase this would mean 1.05x XV@4GHz for 1 thread. So how would turbo headroom, core count, SMT, sth. else change that ratio? I have ideas but want to see yours.
AMD Zen Rumours Point to Earlier Than Expected Release
A german tech publication got wind from a Motherboard manufacturer that we could see new AMD Zen based motherboards as early as March 2016, well ahead of the otherwise known Q4 2016 plan.
The new AMD Zen CPU will use a new socket and also incorporate the current DDR4 capabilities and as such completely new boards have to be designed. In a routine inquiry about this, the publication got a surprising response from the manufacturer. The response: The internal timetable foresees a March 2016 launch. That is a lot sooner than expected.
There are however several ways that this could be both good and bad, true and false. The original Zen timetable has a Q1 2016 schedule that later got pushed. So the company could have been getting the information from old documents. Another possibility could be that we see Opteron CPUs on the new Zen architecture before we get the consumer FX versions around the holiday sales 2016.
Yes, most probably for the XV APUs initially. It will still be interesting to see the AM4 motherboards though, since it's been a while since AMD released a new chipset and the motherboards can be used for Zen too.
That's a Q1 '16 launch for AM4 boards to support the new XV APUs. Zen will not be arriving in Q1'16. Sorry.
Yea, just look at Skylake. Probably what, 4 to 6 months the motherboards were ready before the cpu?
Personally, I dont expect Zen in any kind of good retail supply before 2017. Could be a paper launch earlier though, like core M.
Yes, most probably for the XV APUs initially. It will still be interesting to see the AM4 motherboards though, since it's been a while since AMD released a new chipset and the motherboards can be used for Zen too.
I might pick up a DDR4-using XV APU, just for kicks, if they come out with new boards.
Do you think that we might see USB 3.1 Gen 2 on those boards, by any chance? Or is that pretty-much limited to SKL 1151 boards with Intel's Alpine Ridge controller chipset?
Do you think that we might see USB 3.1 Gen 2 on those boards, by any chance? Or is that pretty-much limited to SKL 1151 boards with Intel's Alpine Ridge controller chipset?
AMD “Promontory” chipset will be rather feature-rich: it will connect to processors using PCI Express 3.0 x4 bus (up to 4GB/s of bandwidth) and will support USB 3.1, USB 3.0 and USB 2.0 ports; one PCI Express 2.0 general-purpose port for various controllers; Serial ATA-6Gb/s and SATA Express port(s). Since “Promontory” platform controller hub (PCH) will rely on a single 4GB/s interconnection to microprocessor, do not expect it to enable a lot of 10Gb/s USB 3.1 ports along with numerous fast SATA Express ports.
Yes, USB 3.1 through the Promontory chipset.
http://www.kitguru.net/components/c...r-direct-nvme-storage-promontory-pch-usb-3-1/
Sounds like it's USB 3.1 Gen 2 compatible since the article mentions 10Gb/s.
Yusuke Ohara discusses Zen's FP throughput and clock frequency:
http://ascii.jp/elem/000/001/088/1088461/index-2.html
(you need a good translator for that )
He sees some special limitation in the fp2 unit/issue port.
From the above, the author has to predict the operating frequency of Zen approximately 3GHz, while Again this is a number in the case of suppressing the SoC of TDP about 60W.
Do not may be of continuous operation about 3.3GHz is possible if Hikiagere up to 90W, and if you use techniques such as Turbo Core is momentarily may not be unreasonable also be pulled up to 4GHz.
So the prediction of 3 GHz is based on the idea of Zen being used in a ~60W TDP SoC. 90W (95W?) would indicate clockspeeds closer to 3.3 GHz. How that interacts with core count is not entirely clear. In any case, the analysis is based on FO4 delay.
It looks like AMD still wants to sell cheap APUs for cheap systems. Who wants to play on iGPU while considering SLI at the same time?That's interesting. So with Summit Ridge you get x16 or two x8 PCIe lanes for dGPU but no iGPU, while if you want the iGPU you're limited to Bristol Ridge and a single x8 PCIe slot? The actual mix of dies and core counts when we see them will be quite interesting, as well as how the MB manufacturers divvy up the lanes.
Edit: Won't Bristol Ridge APUs actually have less considerably less bandwidth than the current FM2+ APUs? With Kaveri you get x16 PCIe 3.0 + x4 PCIe 2.0 lanes from the CPU, along with the x4 PCIe 2 link to the chipset. That list Bristol Ridge as having half the graphics card bandwidth that Kaveri does, and would pretty much eliminate doing SLI on the system.
If the FP description in the patch is correct, throughput of FMAC might indeed be lower. The second FMAC combination (fp1+fp3) might be there to be able to start a staggered FMAC while fp0 got a FMUL.Interesting. He also has this to say (bad translation, but you get the idea):
So the prediction of 3 GHz is based on the idea of Zen being used in a ~60W TDP SoC. 90W (95W?) would indicate clockspeeds closer to 3.3 GHz. How that interacts with core count is not entirely clear. In any case, the analysis is based on FO4 delay.
Not sure what to make of the fp2/fp3 bottleneck.