As long as the motherboard crop that launches in Q1 fully supports Zen, we'll be fine. I might like to get a Bristol Ridge in the meantime, since the 7890k is completely MIA. Not sure I want to part with all this DDR3 so soon, though . . .
So soon? What are you smoking? DDR3 has been available since 2007. My backup PC is runing a I7 920 with 12GB DDR3 from 2008. DDR3 is 'ancient' in technology terms.
If you only just purchased a DDR3 system, then it was a simply silly decision, to invest money in dated technology, then whine about it when DDR4 becomes mainstream.
This part is BS, if 60W are needed at 3GHz then 90W would imply 3.67GHz, the FO4 delay is dependant of the transistors speed, so any estimation done without this parameter evaluated is just wild speculation.
If the FP description in the patch is correct, throughput of FMAC might indeed be lower. The second FMAC combination (fp1+fp3) might be there to be able to start a staggered FMAC while fp0 got a FMUL.
With higher voltages than 0.8V and smart power mgmt it should be no problem to see high burst and also sustained clocks.
So soon? What are you smoking? DDR3 has been available since 2007. My backup PC is runing a I7 920 with 12GB DDR3 from 2008. DDR3 is 'ancient' in technology terms.
If you only just purchased a DDR3 system, then it was a simply silly decision, to invest money in dated technology, then whine about it when DDR4 becomes mainstream.
Uh, huh. I guess you don't agree with the assessment then, despite the fact that it is based on FO4 delays?
Have you um, read the article, or at least a translation thereof? I'll grant that the translation isn't great, and it goes into some territory that's beyond me, but if you don't like what I quoted, well, go check it out for yourself.
Yea, AMD had to do that since Bulldozer and Llano back in 2011. You would be able to start with an APU and then go to an 8-Core and dGPU. Well, we will be able to do that with the FM4 in early 2016 it seems.
The recent rumors regarding the 14nm LPP aren´t too nice to read, especially if the rumor about Apple abandoning the 14nm LPP process in favor of TSMC 16FF Plus due poor yields and worse process characteristics turns out to be true too
16FF+ is selected for the A10. 14LPP is out.
Any source for this?
I also heard Apple cut down the A9 orders from Samsung (in favor of TSMC) and that A9X might be TSMC only.
If all of these rumors are true, then 14nm LPP most likely has failed big time
Any source for this?
I also heard Apple cut down the A9 orders from Samsung (in favor of TSMC) and that A9X might be TSMC only.
If all of these rumors are true, then 14nm LPP most likely has failed big time
He doesnt know what is the FO4 delay of the 14nm process used, so it s impossible to make any estimation, the number of FO4 delays required by the pipeline is simply not enough to have an accurate idea.
The link he uses is ARM Cortex clock frequency at a comparable FO4 pipeline stage depth. He wrote that in his previous article, where he used that method w/o FO4. That's why I looked up that data.This part is BS, if 60W are needed at 3GHz then 90W would imply 3.67GHz, the FO4 delay is dependant of the transistors speed, so any estimation done without this parameter evaluated is just wild speculation.
AMD has voltage droop mitigation. They're also working on near-threshold computing and reliability. God, even asynchronous computing (maybe for GPU shaders) is in the pipeline. The fight for perf/(power*area) goes on.I am interested in seeing if 14nm LPP brings with it higher voltage tolerances than what we see from GF 32nm SOI or 28nm SHP. Broadwell and Skylake give us (slightly) higher voltage tolerances than Intel's 22nm process, for example . . .
Hopefully, AMD will do better with Zen's memory controller.
If that is true, expect a BIG nerf of the A10.... if Apple doesn't add HT or something that improves performance, it will be a dissaster.16FF+ is selected for the A10. 14LPP is out.
The link he uses is ARM Cortex clock frequency at a comparable FO4 pipeline stage depth. He wrote that in his previous article, where he used that method w/o FO4. That's why I looked up that data.
He doesnt know what is the FO4 delay of the 14nm process used, so it s impossible to make any estimation, the number of FO4 delays required by the pipeline is simply not enough to have an accurate idea.
The recent rumors regarding the 14nm LPP aren´t too nice to read, especially if the rumor about Apple abandoning the 14nm LPP process in favor of TSMC 16FF Plus due poor yields and worse process characteristics turns out to be true too
While memory performance is undeniably important for APUs, it isn't anywhere near as critical for CPUs. Still, I do hope Zen can push DDR4 higher than 2400, but it won't concern me it it doesn't.
Still it's ridiculous to launch a DDR4 memory controller limited to DDR4-2400 when DDR4 itself entered the market with modules specced to run DDR4-3200. Even if it's just an overclocking option . . . cmon, man!
i5 6600k spec:
http://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz
Memory Types DDR4-1866/2133, DDR3L-1333/1600 @ 1.35V. Feel free to make a rant thread about it.
Those are only the speeds officially supported by Intel; Skylake's memory multipliers theoretically allow it to go up to something crazy like DDR4-4800 in practice, IIRC. Carrizo on the other hand apparently lacks the multipliers to go any higher than DDR4-2400, so unless Bristol Ridge is a tweaked revision with higher multipliers, that's as high as it's gonna go.
Carrizo on the other hand apparently lacks the multipliers to go any higher than DDR4-2400, so unless Bristol Ridge is a tweaked revision with higher multipliers, that's as high as it's gonna go.
which carrizo motherboards have this limit?
2400MHz is the maximum frequency the IMC can be set to operate. It is impossible to program it for higher ratios, let alone make it operate stable at those frequencies.
Along with the CPU performance itself, the memory controllers are the weakest aspect in AMDs current designs.