[Techpowerup] AMD "Zen" CPU Prototypes Tested, "Meet all Expectations"

[coercitiv]

Why buy XV once it's been announced that Zen is so much faster?

XV is not that bad when TDP is constrained, operating near 3Ghz, it's possible they might go XV mobile for one more generation, especially if they need to ensure some form of continuity for OEMs until Zen based chips arrive.

It would be kind of ironic as well, for their previous gen "big" core to become the next gen "small" core

 

[maddie]

Why buy XV once it's been announced that Zen is so much faster?

I'd just wait for Zen and build new if I wanted to stay with AMD.

I guess a few folks will want to drop an XV chip into an older system, but it doesn't sound like much of an upgrade.

Depends on the price, I guess?

Not everyone wants the highest possible performance, so Bristol ridge would make sense for many.

By the way, Bristol Ridge AM4 model OPN2 has the following specs.
TDP 35W
CPU - Base 3.1 Boost 3.5 GHz
GPU - 900 MHz

Bristol Ridge FP4 model OPN2
TDP 15W
CPU - Base 2.7 Boost 3.6 GHz
GPU - 758 MHz

Carrizo Model FX-8800P
TDP 12-35W
CPU - Base 2.1 Boost 3.4 GHZ
GPU - 800MHz

Question:
Do you really think that these improved speeds, especially the FP4 version,
are possible on 28nm?

 

[The Stilt]

The base clock have different meaning on Carrizo based APUs than on other products. Both CPU and GPU speeds will drop below their "base clocks", depending on how much power is consumed.

IIRC the CPU cores on FX-8800P drop down to 1.8GHz when the GPU is fully utilized. And the default TDP for FX-8800P is 15W / 18W / 25W (base, battery boost, boost).

 

[coercitiv]

Do you really think that these improved speeds, especially the FP4 version, are possible on 28nm?

If those benchlife slides are true, then base speed got a surprisingly big boost. I guess we'll find out more soon.

 

[mrmt]

It would be kind of ironic as well, for their previous gen "big" core to become the next gen "small" core

Not irony, more like desperation.

 

[DrMrLordX]

The base clock have different meaning on Carrizo based APUs than on other products. Both CPU and GPU speeds will drop below their "base clocks", depending on how much power is consumed.

IIRC the CPU cores on FX-8800P drop down to 1.8GHz when the GPU is fully utilized. And the default TDP for FX-8800P is 15W / 18W / 25W (base, battery boost, boost).

It remains to be seen how much of that behavior carries over to a desktop chip like Bristol Ridge. Those chips ought not throttle unless they overheat or go past the vrm/socket power constraints. A system with good VRMs, a solid socket, and nice cooling should prevent any throttling, which was an annoying but circumnavigable flaw of desktop Kaveri. Bristol Ridge does not need to exhibit the same behavior.

But, all the same, those TDP ratings may depend on that behavior. So I would like to see power draw measurements in a game or something at a static clockspeed vs. Kaveri refresh. Then we'll learn the true measure of the chip.

 

[Dresdenboy]

What if AMD included their IVR components into the new packages?

That could explain the BR jump.

 

[The Stilt]

There is no IVR for Bristol Ridge or Zen (thank god). IVR in it´s current for is just a huge waste of power with not too many, if any real advantages. Probably the reason why Intel got rid of it in Skylake.

First you´ll have the PSU, which converts the AC to DC (12V) which is fed to the VRM. That conversion can be made with ~94% efficiency on modern PSUs.

Then the 12V input voltage must be step-down to ~1.8V which is FIVR input voltage. The efficiency of the motherboard VRM will be rather poor since the output voltage required by the FIVR is relatively high (1.0 NPL @ 1.2V, 1.25 NPL @ 1.8V).

Then the FIVR input voltage will be again step down by the FIVR itself. The efficiency of FIVR is extremely poor since it must operate at extremely high switching frequencies, due the extremely tiny integrated inductors / low capacitance. Normally a motherboard VRM operates at 200-800kHz switching frequency, however FIVR operates at 175-700 times higher switching frequency (140MHz). This results in extremely poor efficiency, and according to Intel the first FIVR implementations had efficiency of ~78%.

So basically all that FIVR does is adding an extra step-down phase, which increases the switching losses even further.

AM4 has two main high current power planes, same as AM3+ or FM2+.

 

[ShintaiDK]

The FIVR is only out of Skylake because Core M power levels couldn't be reached due to time constrains. Its back in Skylake-E and Icelake.

 

[Fjodor2001]

http://wccftech.com/amd-zen-successors-several-designs-in-development/

AMD’s Zen CPU Has Several Successors In The Works – Multiple Zen+ Generations Planned Over 3 To 5 Years

AMD’s CEO Lisa Su confirmed that the company is working on several generations of CPUs to succeed Zen which are set to arrive over the next 3 to 5 years. These future CPU cores and microarchitectures were referred to by the CEO as “Zen+” and Zen follow ons.
[...]

Credit Suisse 19th Annual Technology, Media & Telecom Conference

John Pitzer :
"When you think about your datacenter efforts how important is Zen next year?"

Lisa Su, President & CEO of AMD :
"I think Zen is the first of a multi-year strategy so you know again you ask me what are my thoughts around the company I think AMD at our core we are a high performance computing company and so you know Zen is a from scratch architectural design, for those of us who do those you know it takes a lot of work. It’s a multi-year effort but I think it’s a multi-year effort that we can see coming to fruition. And so what datacenter customers want from us is one we want you to be competitive and two we want a long term roadmap. And so we’ve really talked about Zen+, Zen follow ons, as you know a three to five year view of what’s needed to be successful in the datacenter."

[...]

Zen sampling is set to start next year with initial availability by the end of 2016 and broader market reach by 2017.

 

[Tuna-Fish]

Well, duh. Going from a blank slate to a released product takes ~5-6 years, and has many stages typically worked on by different teams. All the CPU makers maintain their product cadence by having different teams work on different parts of successive designs in parallel (and Intel goes further than that and has two full sets of design teams working on alternate archs), if they didn't have new CPUs in the pipeline for after Zen it would mean that their high-level team would have done nothing for 4 years.

This is why disasters in CPU design take so long to solve -- by the point Intel had actual performance numbers out of Willamette, the design of Northwood and Prescott were both finalized and Tejas was being worked on. Same goes for AMD with BD.

Zen+ and Zen++ are improving what the designers think are the biggest downsides of Zen. Like always, they won't even know if the basic design makes any sense or what the real bottlenecks are until too late.

 

[Phynaz]

AMD is making another CPU after Zen.

Put the obvious on a web page and people quote you.

 

[LTC8K6]

"Zen isn't all that good, and we had to fix it quickly with a Zen+."

 

[III-V]

"Zen isn't all that good, and we had to fix it quickly with a Zen+."

Heh, I'm concerned that their time-to-market constraints will have left a lot on the table. Still, I have fairly good expectations for Zen -- I can't imagine they went with a radical new design. I expect them to make an Intel-like design.

 

[looncraz]

"Zen isn't all that good, and we had to fix it quickly with a Zen+."

Zen won't be all that great compared to the core's potential. Zen ver 1 is very obviously an attempt at creating a simple wide core that takes care of only the lowest hanging fruit.

They reused every bit of IP they could, quite possibly even using a revised Stars cache system.

The core design should be good for a good near-doubling of performance over Excavator (integer anyway), but they have obviously not made all the effort to see that done for the first Zen. Zen+ will have another 15%, and they will probably be able to get that much out of it for several more revisions.

One important thing to know is that they probably only have a fair idea of where the bottlenecks really are. Simulations can't predict what software will become the most important in the future - something which really hurt AMD with Bulldozer. Zen looks to go in the exact opposite direction - it is a very generically optimized core designed for current programs with almost no regard for future programs. That is a GREAT start for AMD.

AMD has a bad habit of planning for a future that does not come for many many years (if ever at all). GCN is a fantastic example of this - AMD included asynchronous shaders (at a pretty meaningful power cost) just because they thought it'd be useful one day. nVidia, meanwhile, focused on working as well as they could for games that already were in the wild. The result is that AMD has unusable hardware sucking up power, and nVidia has an efficient GPU. The flip side is that all GCN GPUs are DirectX 12 capable - and quite powerful with it, and nVidia is still trying to get there.

But that doesn't get you sales. It actually hurts sales. A lot.

AMD needs to get into the habit of planning for the current software, rather than trying to direct the future (except with their open source software and standards initiatives, where they can really make an impact).

 

[Dresdenboy]

"Zen isn't all that good, and we had to fix it quickly with a Zen+."

Welcome to a resource constrained world of costly and complex multi year projects in an economic world. Why did Intel bother developing the Pentium Pro, just to extend the concept later until Skylake and it's successors?

Heh, I'm concerned that their time-to-market constraints will have left a lot on the table. Still, I have fairly good expectations for Zen -- I can't imagine they went with a radical new design. I expect them to make an Intel-like design.

If they'd try to cram their whole roadmap into the first product, they'd miss later process nodes (which also help with improving or adding uarch features) and TTM would be prolonged to maybe 2019-2020. Their latest statement shows some confidence in living that long. They should check the forums, where according to the experts there knowing the Zen roadmap, AMD won't survive a year or two.

So far they cancelled other projects to focus on Zen. But as the CPU development cycle goes, they'd have had to leave the uarch features on the table already in 2013. What they did the last quarters is timing-closures, validation, verification, bugfixing (pre-silicon as long as they didn't make test wafers).

Zen won't be all that great compared to the core's potential. Zen ver 1 is very obviously an attempt at creating a simple wide core that takes care of only the lowest hanging fruit.

They reused every bit of IP they could, quite possibly even using a revised Stars cache system.

The core design should be good for a good near-doubling of performance over Excavator (integer anyway), but they have obviously not made all the effort to see that done for the first Zen. Zen+ will have another 15%, and they will probably be able to get that much out of it for several more revisions.

One important thing to know is that they probably only have a fair idea of where the bottlenecks really are. Simulations can't predict what software will become the most important in the future - something which really hurt AMD with Bulldozer. Zen looks to go in the exact opposite direction - it is a very generically optimized core designed for current programs with almost no regard for future programs. That is a GREAT start for AMD.
[...]
AMD needs to get into the habit of planning for the current software, rather than trying to direct the future (except with their open source software and standards initiatives, where they can really make an impact).

Enjoy the old and fight the new?

Some average 40% improvement (likely better for int and lower for FP) as a first simple wide core would be interesting. Well, I think, they already put some effort into it, as it is difficult to add necessary complex components later. That would be like creating another core from scratch around the existing bunch of ex units.

Zen+ might remove any possible FP throughput deficiencies (if there are some) - instead of going 256b wide. This would make the core somewhat bigger. Power increase could be mitigated by further tuning of other components.

Stars cores cache system is unlikely, as there is too much influence between that and the other parts of the uarch.

 

[Dresdenboy]

There is no IVR for Bristol Ridge or Zen (thank god). IVR in it´s current for is just a huge waste of power with not too many, if any real advantages. Probably the reason why Intel got rid of it in Skylake.

First you´ll have the PSU, which converts the AC to DC (12V) which is fed to the VRM. That conversion can be made with ~94% efficiency on modern PSUs.

Then the 12V input voltage must be step-down to ~1.8V which is FIVR input voltage. The efficiency of the motherboard VRM will be rather poor since the output voltage required by the FIVR is relatively high (1.0 NPL @ 1.2V, 1.25 NPL @ 1.8V).

Then the FIVR input voltage will be again step down by the FIVR itself. The efficiency of FIVR is extremely poor since it must operate at extremely high switching frequencies, due the extremely tiny integrated inductors / low capacitance. Normally a motherboard VRM operates at 200-800kHz switching frequency, however FIVR operates at 175-700 times higher switching frequency (140MHz). This results in extremely poor efficiency, and according to Intel the first FIVR implementations had efficiency of ~78%.

So basically all that FIVR does is adding an extra step-down phase, which increases the switching losses even further.

AM4 has two main high current power planes, same as AM3+ or FM2+.

As AMD has IVR on their roadmap for 2016 and I don't expect a new socket in 2017-2018, they might include it in the near timeframe. Like Shintai said, Intel will continue using it. So the benefits likely outweigh any efficiency concerns. According to
http://www.hotchips.org/wp-content/...23.17.111.Practical_PGandDV-Kosonocky-AMD.pdf
there seems to be an efficiency of 90% at specific ratios (slide 26). As Kosonocky is favouring Buck converters, slide 28 shows some efficiency values for them with integrated and separate inductors. There's also a 70% efficiency line, suggesting some importance. Depending on the currently reachable levels, increasing amount of voltage islands, and achievable power savings due to high frequency regulation, there might be a sweet spot supporting IVRs even at lower efficiency levels.

And AMD might integrate the capacitors into the package layers:
http://www.google.com/patents/US20130257525

More here:
http://powersoc2012.org/session-6/6.4_Steve.Kosonocky.pdf

 

[mrmt]

The core design should be good for a good near-doubling of performance over Excavator (integer anyway), but they have obviously not made all the effort to see that done for the first Zen. Zen+ will have another 15%, and they will probably be able to get that much out of it for several more revisions.

 

[looncraz]

Enjoy the old and fight the new?

Some average 40% improvement (likely better for int and lower for FP) as a first simple wide core would be interesting. Well, I think, they already put some effort into it, as it is difficult to add necessary complex components later. That would be like creating another core from scratch around the existing bunch of ex units.

Zen+ might remove any possible FP throughput deficiencies (if there are some) - instead of going 256b wide. This would make the core somewhat bigger. Power increase could be mitigated by further tuning of other components.

Stars cores cache system is unlikely, as there is too much influence between that and the other parts of the uarch.

They've obviously removed some logic from the ALUs and provided better specialization of the ALUs to distribute resources appropriately, but each of these IP blocks are undoubtedly just copy, pasted, and adapted from the Excavator database. The decoders may be exact copies of Bulldozer's, with barely even any changes at all. Each stage of the pipeline will probably be the same, with the exception of how instructions are dispersed.

It would not surprise me at all if Zen had most, or even all, of the front-end pipeline stages from the construction cores. They wouldn't need to worry as much about how long each stage took thanks to faster switch transistors, so they may even plan on merging a stage or two (assuming they haven't done so). This would help them reach higher clocks as well, which is very critical for their competitiveness.

I would be surprised if they did that, of course, and didn't mitigate the branch misprediction penalty (but part of that is due to cache latency, so it will be reduced no matter what).

As for my comment about using the Stars' cache, I meant, specifically, the memory design itself, not the integration with the core.

 

[moonbogg]

Every time I see the words in the thread title "Meets all expectations" I can't help but laugh a little inside. Those words would make such a wonderful punch line should the CPU fail. I personally hope it does well, but I can't help but see an opportunity for some serious laughs if things go wrong.

 

[Fjodor2001]

Every time I see the words in the thread title "Meets all expectations" I can't help but laugh a little inside. Those words would make such a wonderful punch line should the CPU fail. I personally hope it does well, but I can't help but see an opportunity for some serious laughs if things go wrong.

Do you prefer that Intel hailed Skylake as "its most important chip architecture in a decade"... Now how ridiculous wasn't that!

 

[Arachnotronic]

Do you prefer that Intel hailed Skylake as "its most important chip architecture in a decade"... Now how ridiculous wasn't that!

Skylake was really good unlike the AMD trash that's currently in the market. It brought a solid boost in CPU perf and major enhancements elsewhere in the SOC, particularly in media.

 

[Phynaz]

Do you prefer that Intel hailed Skylake as "its most important chip architecture in a decade"... Now how ridiculous wasn't that!

It isn't?

What chip has been more important?

 

[Sweepr]

Skylake was really good unlike the AMD trash that's currently in the market. It brought a solid boost in CPU perf and major enhancements elsewhere in the SOC, particularly in media.

Also let's puts some context here.

“When I look at the range of what Skylake’s able to deliver from the Core M level all up to the i7 and Xeon, it’s just going to be a fantastic product,”

 

[MrTeal]

It isn't?

What chip has been more important?

Core 2.

Edit: I'd also say SB was a larger step over Nehalem than Skylake was over Haswell. We'll have to wait and see whether SL-E over HSW-E is a bigger step than SB-E was over Gulftown.