The disappointing slowdown CPU progress in last 6 years vs 4 years before (10 yrs) ago

[Nothingness]

PIPT is not really an options for L1$ unless you want to lose performance.

My point mainly was that recent 64-bit ARM CPU have hardware anti aliasing for their VIPT caches. This is made explicit in Linux kernel source: https://elixir.bootlin.com/linux/v5.2-rc5/source/arch/arm64/include/asm/cache.h#L73

/*
* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
* permitted in the I-cache.
*/

EDIT: Sorry @Thala I missed your last answer

 

[Thala]

My point mainly was that recent 64-bit ARM CPU have hardware anti aliasing for their VIPT caches. This is made explicit in Linux kernel source: https://elixir.bootlin.com/linux/v5.2-rc5/source/arch/arm64/include/asm/cache.h#L73


EDIT: Sorry @Thala I missed your last answer

No problem, i had to quickly look this up in ARM ARM, because i was not 100% sure if the architecture is really restricting here - but it turned out that you were right

If i remeber correctly MIPS R4x00 has aliasing VIPT caches for example and the OS is handling this via page coloring.

 

[Nothingness]

If i remeber correctly MIPS R4x00 has aliasing VIPT caches for example and the OS is handling this via page coloring.

Yes and quickly browsing Linux kernel, it looks like some SPARC also has such data caches.

 

[Spartak]

To the OP: single core performance has slowed down over the last 5 years but Sunny Cove and Zen 3 next year will finally change that. Multi-core performance has seen a continuous improvement but I'm expecting that to slow down somewhat as well. There's only so many cores you can effectively use, and all-core frequencies are inching towards single core max as the 9900KS has shown.

IPC will become essential for both single core and multicore improvements moving forward.

 

[Systems analyst]

Core-count does matter, when parallelising an algorithm. The Wolfram language allows easy parallelisation using, for example:
cP = Compile[{{x}}, x^2, RuntimeAttributes -> {Listable},
Parallelization -> True]
This is automatically queued and run across all kernels, one per core, when the function is invoked.
It is surely better to have as many cores as practical on one SoC, to minimise overheads, as computation features alternating phases of parallel computation and serial computation, bringing together the results of parallel threads.
ARM already provide IP for up to 64 cores in a SoC, and are working on 128 cores per SoC. Also, the advent of SVE is allowing a degree of parallelisation within a cycle
In other words, both software and hardware are advancing to increase the degree of parallelisation available to the algorith designer, and blurring the meaning of IPC.
These developments increase computing-power by pushing in the directions of most 'give', and will mitigate any limits in scaling of silicon.

 

[A///]

That seems like a gross oversimplification. Would be easy to change the TDP and take over the desktop market as well as the mobile one. As another poster said, it is basically an apples to oranges comparison, since they dont run x86.

Yeah, and he seemed to ignore what I asked. What he said isn't relevant to x86-64 processors at all. The proponents of ARM say it'll use less power and output less heat. redacted[-/b]. It'll use just as much. ARM isn't some magical bean they gave Jack.




No profanity allowed in the technical forums.


esquared
Anandtech Forum Director

 

[PsiStar]

Don't focus too much on clock speed. Take PCIe for instance. Gen3 clock rate is higher than the data rate. Gen5 the data rate is higher than the clock rate. Actually that started with Gen4, but who cares about intermediate tech?

The important issue is the the lower clock rate or lower RF bandwidth needed of the higher speed data channels greatly reduces the physical requirements of the channel ... loss in the PCB dielectrics & smoothness of copper traces do not have to be as low or as smooth (==$$).

Higher RF bandwidth causes a lot of noise in the the chips + PCBs. So there has to be a higher level of engineering on the cpu chips before the RF bandwidth can go up. The current bandwidth meets the capability of the current chip structure .. figure there is a cost factor on that balance.