It is disappointing to me because those 16 EUs are goiing to drive up cost.
P.S. Not sure how much die size it takes up but I would rather have an Intel LAN integrated on die than a 16 EU iGPU for utility laptop and economy mini-desktop.
Why it is disappointing? Haswell GT1 has 10 EUs. 16 EUs would be pretty high for this SoC. We don't have a confimation for EU count on Cherry View/Braswell.
It is disappointing to me because those 16 EUs are goiing to drive up cost.
P.S. Not sure how much die size it takes up but I would rather have an Intel LAN integrated on die than a 16 EU iGPU for utility laptop and economy mini-desktop.
ARM SoCs GPUs are getting better and better, so Intel needs to also keep improving their IGPs, if they want to compete.
Braswell is lowcost so I wouldn't worry about the price. I don't see cost issues from 16 EUs on 14nm. It's a good sign that Intel takes their iGPU serious finally. But once again, we don't know how much EUs CHV/Braswell gets.
Bay Trail is 102mm2.
To me that already is a rather large chip for something meant to be low cost.
And looking at the following die shot , its 4EUs seems to take up quite a bit of die area realestate already:
........ 14nm will allow Intel to put in more EUs but iif that number is 16 I'd imagine the die will remain fairly large.
As I understand it a lot of pre-existing x86 software runs fine without a large iGPU.
I take it you mean in the same power bracket, right?as long as braswell doesnt have lower EUs compared to haswell GT1 it should be fine. it will have faster CPU and iGPU from anything ARM or AMD
Assume your wafer costs $3200, your yields are 90%, and die size is roughly square.
This implies ~586 die/wafer and 527 good die per wafer. $3200/527 = $6. Add in a buck or two for packaging and test, and you've got a $7-$8 chip to make.
Pretty cheap chip. Sell that sucker for $20 and you've got ~60% GM. It only gets better as the chips get more integrated and as Intel optimizes its designs for density.
Really, the economics of this are pretty fantastic for Intel. Increase your wafer cost by 22% for 14nm (this is the number given @ investor meeting) but then move your die size to ~60mm^2, again roughly square, and let's call it 80% yield and what do you get?
$3904 wafer -> 764 dies per wafer. 611 good die per wafer come out of the oven. Add again $1-$2 for packaging and test, and viola you've got a $7.50-$8.50 chip even if you assume materially worse yields.
Sell that sucker for $20 and once again, you've got high 50% GMs. Can't wait to hear how the "Intel sux" brigade wants to spin that ;-)
Broxton should be 58mm², which is quite good for a high-end tablet+phone SoC (Apple's A7 is also 102mm²). Cherry Trail could be sub-50mm².
Nice, I was at the second line thinking who was doing this extensive calculation and obviously it was you .
Yesterday I read an article (The Status of Moore's Law: It's Complicated) that states that the scaling of 22nm (from 32nm) was limited by the fact that Intel uses single patterning for the metal wires, while 20nm will use double patterning. So the metal layer pitch will be 80nm vs. 64nm, which is why Intel's 22nm isn't as dense as 20nm:
So that explains why Intel is aggressive on scaling at 14nm, going to a density of what TSMC would've called 16nm if they didn't take a scaling pause to implement FinFET.
My bet is that they didn't see 64-bit Apple coming that quickly along with Intel.On a side note, quite surprising to see Qualcomm using ARM-designed cores. Makes me wonder if they're having issues with their own design and this is the backup plan.
Yes.
But:
1) pretty tablet OSes use a lot more GPU than WinXP did, with all their swiping and stuff. And the screens are crazy-highres, which means more pixels to push. (1080p displays or larger are typical on "nice" tablets.)
2) primary things tablets and phones are used for are web browsing, multimedia playback, and gaming. Two of those three things benefit from some GPU oomph behind them.
Performance in the GPU space has been increasing faster than in CPUs.
We're talking about a mobile SoC that hasn't even come out yet - it's gotta be the chip the market wants a year or two from now, not necessarily the chip that would be best price/perf for running a Win7 desktop now.
Assume your wafer costs $3200, your yields are 90%, and die size is roughly square.
This implies ~586 die/wafer and 527 good die per wafer. $3200/527 = $6. Add in a buck or two for packaging and test, and you've got a $7-$8 chip to make.
Pretty cheap chip. Sell that sucker for $20 and you've got ~60% GM. It only gets better as the chips get more integrated and as Intel optimizes its designs for density.
Really, the economics of this are pretty fantastic for Intel. Increase your wafer cost by 22% for 14nm (this is the number given @ investor meeting) but then move your die size to ~60mm^2, again roughly square, and let's call it 80% yield and what do you get?
$3904 wafer -> 764 dies per wafer. 611 good die per wafer come out of the oven. Add again $1-$2 for packaging and test, and viola you've got a $7.50-$8.50 chip even if you assume materially worse yields.
Sell that sucker for $20 and once again, you've got high 50% GMs. Can't wait to hear how the "Intel sux" brigade wants to spin that ;-)
@Khato - i dont think its design issues. i think its the quicker way to release a 64 bit high end soc instead of waiting for their own design to complete
@Khato - i dont think its design issues. i think its the quicker way to release a 64 bit high end soc instead of waiting for their own design to complete
My bet is that they didn't see 64-bit Apple coming that quickly along with Intel.