I'm not certain, but I think it is LP? HPM would make sense as well but I'm not sure how well that would fly at the lower end. Given the big bump in TDP for the relatively meager bump in clock speeds between the lowest Temash and the highest Kabini, I'd wager LP.
Check out these AMD slides, page 7 reveals a bit about the process:
http://www.hardware.fr/marc/ISSCC2013-Final-v5.pdf
TSMC's 28LP process doesn't use HKMG so it can't be that. They also say that only HVT, RVT, and LVT transistors were used. And on page 28 they say this:
Primary design optimization uses all Low Vt for speed and area.
So that says pretty much outright that their design isn't leakage optimized. And this is consistent with the idle power consumption being not very good at all - AMD themselves say > 1W for the 4 core parts. That would be mostly leakage.
Also, to those saying that it may still be able to clock much higher than 2GHz, they say outright that they achieved "> 1.85GHz", meaning 2GHz in well binned parts is probably not leaving an awful lot on the table (hoping no one chimes in to tell me that they could have meant much much greater than 1.85GHz by that statement ).
They do say there's an emphasis on density, maybe if they optimized performance at the expense of density they could have gotten more clock speed. Although from what I've heard a lot of area and timing optimizations go hand in hand, as you'd expect from decreasing average wire length between sections, although you can pretty easily think of cases where that wouldn't be true.
Qualcomm has stated their Snapdragon 800 can clock up to ~2.5ghz on TSMC's HPm.
Not to nitpick, but those cores (or Krait 300, almost the same thing anyway) are clocking fine at 1.9GHz in the 28LP Snapdragon 600 (as seen in Galaxy S4s). But yes, Qualcomm has made it very clear that changes in process allowed for higher clocks.