The Ryzen "ThreadRipper"... 16 cores of awesome

[The Stilt]

Had a look at the production bios of EPYC 1P board. ZP-B2 is using it's own µcode version, which usually implies that there are at least some actual differences in the silicon. Still need to check if ZP-B1 can work with this µcode version.

There should be no reason why EPYC (compared to consumer Ryzen's / TR) would require different die revision, unless there were issues in something xGMI related (only used in 2P, i.e EPYC).
In any case if the ZP-B2 stepping is a real deal and not a "marketing stunt" to differentiate the consumer and server parts more apart each other, we should start to see ZP-B2 being used in consumer parts pretty soon as well. It would be completely idiotic to have
two feature wise identical die revisions in production. Especially when that is the completely opposite to what AMD has been doing so far with Zeppelin.

 

[tamz_msc]

Had a look at the production bios of EPYC 1P board. ZP-B2 is using it's own µcode version, which usually implies that there are at least some actual differences in the silicon. Still need to check if ZP-B1 can work with this µcode version.

There should be no reason why EPYC (compared to consumer Ryzen's / TR) would require different die revision, unless there were issues in something xGMI related (only used in 2P, i.e EPYC).
In any case if the ZP-B2 stepping is a real deal and not a "marketing stunt" to differentiate the consumer and server parts more apart each other, we should start to see ZP-B2 being used in consumer parts pretty soon as well. It would be completely idiotic to have
two feature wise identical die revisions in production. Especially when that is the completely opposite to what AMD has been doing so far with Zeppelin.

Could the actual errata fixes be related to the as yet unknown bug(s) causing GCC segfaults?

 

[VirtualLarry]

In BOINC, running NFS@Home project, the "15e" tasks, seem to error out ("Computation Error") on Ryzen 5 for some reason. Unknown cause at this point.

I'm not the only one with a Ryzen on the TeAm having the issue.

Hopefully this gets looked at by AMD.

 

[The Stilt]

Could the actual errata fixes be related to the as yet unknown bug(s) causing GCC segfaults?

Don't they affect Ryzen / Threadripper as well?

 

[funks]

Don't they affect Ryzen / Threadripper as well?

It's fairly easy to reproduce it now (without having to install Linux on the HDD by using the LiveUSB instead). Both my Asrock Taichi X370 (with 1700X) and the GIgabyte AB350 Gaming 3 (with 1700) is affected. Disabling uop cache allowed the Taichi to compile GCC 7.1 in a bootloop for 12 hours straight, usually fails within the first or second iteration. Took a while longer to fail on the Gigabyte board, but there's no uop cache "disable" exposed by Gigabyte.

I don't think anybody at this point know what revision thread ripper is, probably B2 as well. AMD needs to get cranking on finding the root cause, pretty sure enterprise's won't touch these chips especially if it has a problem running Linux (ESX-Hosts), or running Linux VM's.

 

[funks]

In BOINC, running NFS@Home project, the "15e" tasks, seem to error out ("Computation Error") on Ryzen 5 for some reason. Unknown cause at this point.

I'm not the only one with a Ryzen on the TeAm having the issue.

Hopefully this gets looked at by AMD.

Tried disabling both SMT and uop cache?

 

[tamz_msc]

Don't they affect Ryzen / Threadripper as well?

Yes, that is why it's important that we know what the actual differences are between B1 and B2 and whether TR and EPYC are B1 or B2.

 

[VirtualLarry]

Possibly these errors, are why AMD was initially marketing their Zeppelin-die-based products to "Gamers". Because, why should gamers care about "errata"?

 

[scannall]

Possibly these errors, are why AMD was initially marketing their Zeppelin-die-based products to "Gamers". Because, why should gamers care about "errata"?

Every CPU initially has some amount of errata when released. CPU's and their attendant process technologies are arguably the most complex things ever designed by human beings. It would be a miracle to come out with a perfect CPU on the first pass. Particularly with a brand new uarch to boot. Consumers typicaly get the first pass, then the more demanding enterprise enviornment gets the later ones where the errata is spotted and fixed in silicon, not just in microcode.

 

[The Stilt]

Yes, that is why it's important that we know what the actual differences are between B1 and B2 and whether TR and EPYC are B1 or B2.

The point was, that if the ZP-B2 is a real deal and contains errata fixes, why would AMD still release Threadripper using the old "flawed" die revision?

 

[CatMerc]

The point was, that if the ZP-B2 is a real deal and contains errata fixes, why would AMD still release Threadripper using the old "flawed" die revision?

Clear out existing stock is all I can think of.

There's also the possibility that maybe B2 is just the mirrored die we've seen in EPYC slides?

 

[The Stilt]

Clear out existing stock is all I can think of.

There's also the possibility that maybe B2 is just the mirrored die we've seen in EPYC slides?

Except there isn't any old stock in the chanel for Threadripper.

 

[Topweasel]

Clear out existing stock is all I can think of.

There's also the possibility that maybe B2 is just the mirrored die we've seen in EPYC slides?

It could be. Either way people talk waaaaay too much about the B2 stepping. The few times that it actually lead to decent sized improvement (Phenom I and Thuroughbred) didn't even get this kind of analysation. It's highly unlikely that B2 is anything worth talking about.

 

[mattiasnyc]

Except there isn't any old stock in the chanel for Threadripper.

Well, couldn't there be old stock dies in the channel so to speak? Meaning not the actual CPUs, but the dies the different models all share.

 

[Slappi]

So when will I be able to buy a threadripper in retail?

 

[scannall]

So when will I be able to buy a threadripper in retail?

Should be available retail August 10th.

 

[Ajay]

The point was, that if the ZP-B2 is a real deal and contains errata fixes, why would AMD still release Threadripper using the old "flawed" die revision?

I hope they don't. There have been some rumors that the TR release is delayed due to supply issues. Hopefully it's a matter of having to ramp up ZP-B2 wafers for EPYC and TR so that TR isn't a 'paper' release.

 

[crashtech]

In BOINC, running NFS@Home project, the "15e" tasks, seem to error out ("Computation Error") on Ryzen 5 for some reason. Unknown cause at this point.

I'm not the only one with a Ryzen on the TeAm having the issue.

Hopefully this gets looked at by AMD.

I feel like I ought to correct the record here. Initially I saw the problem on my 1700X, but as it turns out, every CPU I had on the project had at least some errors on the 15e task. The difference was that the Ryzen errored out on every single task, while the other CPUs were able to complete 40-50% of them without error. But it is clearly a problem with the app and not the CPU, imo.

 

[VirtualLarry]

But it is clearly a problem with the app and not the CPU, imo.

Well, that's good to hear. I only have Ryzen rigs crunching here, and I saw the issue on most all of them.

I thought that it could have been my new DDR4-3000 Team Vulcan RAM, but the "16e" tasks which take up to 1GB RAM each, seem to be completing fine on all of the rigs.

 

[mattiasnyc]

according to wccftech this is confirmed now:

 

[richierich1212]

Hardware unboxed said Pre-orders for TR will be up tomorrow, July 31st. Newegg links should be up soon.

 

[VirtualLarry]

Maybe I should sell my two "spare" Ryzen 5 1600 rigs, and get a 16-core TR setup? Nah...

 

[.vodka]

http://www.anandtech.com/show/11678...1920x-august-10th-new-1900x-549-usd-august-31

Is CPU-z misreporting the stepping here, reading from its database or something? Isn't TR supposed to be B2 like Epyc?

 

[tamz_msc]

Still hoping for them to announce the non-X versions.

 

[The Stilt]

http://www.anandtech.com/show/11678...1920x-august-10th-new-1900x-549-usd-august-31

Is CPU-z misreporting the stepping here, reading from its database or something? Isn't TR supposed to be B2 like Epyc?

You can't misreport the stepping version, as it is determined from the CPUID registers (x1, EAX).
Stepping (x1 EAX 3:0): 1 = ZP-B1, 2 = ZP-B2.