The Ryzen "ThreadRipper"... 16 cores of awesome

[TheGiant]

If you really think about the existence of the 1800x and it's $500 pricing actually increases the attractiveness of Ryzen and the 1700 in general. Keep the 1700 at $330 and remove the 1800x and I am willing to bet the 1700 doesn't sell as well. Offering the 1700 while the 1800x exists makes the 1700 look like a fantastic deal since you can get it and clock it up to a 1800x clock speed. Making your $300 run like a $500 chip. The 1800x made a $300 dollar chip seem like a fantastic deal and if you can't see how that helps and doesn't hurt AMD I don't know if I have anything else to say.

don't get me wrong, I am not fighting with you, you summarized it nicely. it is all about relativity. What if every 6C+ ryzen was 50USD higher? Nothing would happen. Some ppl will buy 6C instead of 8C but AMD will retain standard for 8C.

TR must be priced relatively ok to mainstream ryzen. I think if AMD just made the standard price higher of 30-50USD they could make a lot of money and they need the money more than any other chip designer.

We are on this forum talking mainly in exact numbers and quite big objectivity. But the general crowd doesn't. That where the money is.

But please stop this discussion.

I am looking forward to buy TR for my CFD jobs. My 14C BDW Xeon needs a buddy

 

[dlerious]

Is that from the wall or CPU because I was reading 4.1 at 1.35 was closer to 140w CPU only. The upper end if the overclock is going to be a little less predictable because of the heavy difference in voltage needed to sustain the speed. Binning plays a heavy part in it as well a 1700 die could hit 3.9 but it's probably going to need more voltage and cooling than a die used for the 1800x.

I'll have to download HWInfo and see what my 1800X is pulling at 3.9 all-core 1.35v . There was a chart floating around from Silicon Lottery bining results showing clock speed and voltage as well as % of chips hitting that. Found it. The 1800X has the best chance at the lowest voltage at each step, followed by 1700X, then 1700.

Ryzen 7 1700
93% reach 3.8GHz @ 1.376V
70% reach 3.9GHz @ 1.408V
20% reach 4.0GHz @ 1.440V

Ryzen 7 1700X
100% reach 3.8GHz @ 1.360V
77% reach 3.9GHz @ 1.392V
33% reach 4.0GHz @ 1.424V

Ryzen 7 1800X
100% reach 3.8GHz (assumed)
97% reach 3.9GHz @ 1.376V
67% reach 4.0GHz @ 1.408V
20% reach 4.1GHz @ 1.440V

 

[dnavas]

Is that from the wall or CPU because I was reading 4.1 at 1.35 was closer to 140w CPU only.

That's what HWInfo (?) reads. My system closes in on 250W from the wall. I don't recall idle off the top of my head, but I think I was seeing something like 50-60W from the wall, which I was really impressed by (my previous i860 was more like 95, and my NAS when the HDs are idle is pulling that kind of power). I never got a boot at 4.1, although I stopped upping voltage a little over 1.4. I assume 3.8 is about tops for TR, although I'll be more than happy to be shown wrong.

 

[Topweasel]

That's what HWInfo (?) reads. My system closes in on 250W from the wall. I don't recall idle off the top of my head, but I think I was seeing something like 50-60W from the wall, which I was really impressed by (my previous i860 was more like 95, and my NAS when the HDs are idle is pulling that kind of power). I never got a boot at 4.1, although I stopped upping voltage a little over 1.4. I assume 3.8 is about tops for TR, although I'll be more than happy to be shown wrong.

3.8 is likely the top general point of OC's but I get my debate with you is that the limit will be the lowest common denominator in Zeppelin dies limits and not anything else even CPU power usage even bordering on 200w at 4-4.1 (not sold that this is the actual case on the really good dies). The chance will be more ridiculously small. I just don't think thermals, interconnect, or power usage will affect the top clocks of TR as it does on SL-X. SL-X is much higher power usage per core, has bad thermal transfer to the HSF, and runs extremely hot.

 

[DrMrLordX]

I would figure 3.6 base minimum they'd be able to sort out. My 1700 does 3.65 without bumping volts. CPU-Z shows 1.2v under full load (if it's being accurate).

Yeah that's what I was thinking. The power draw from 3.0 - 3.6 GHz is . . . well it's not identical, but it doesn't change much. The current iteration of Zen on the current LPP process seems to start in with the massive power draw beyond somewhere around 3.6 GHz.

 

[DeeJayBump]

... it is all about relativity. What if every 6C+ ryzen was 50USD higher? Nothing would happen. Some ppl will buy 6C instead of 8C but AMD will retain standard for 8C.

TR must be priced relatively ok to mainstream ryzen. I think if AMD just made the standard price higher of 30-50USD they could make a lot of money and they need the money more than any other chip designer.

AMD appears to be selling significant volume of desktop Ryzens. Based on the rumored cost per [$50-60 per for Ryzen then X2 for Threadripper and X4 for Epyc] Zeppelin to manufacture/test/package them, coupled with the rumored [Over 80%, with 95% or more of produced chips per wafer capable of being sold in some SKU] yields, "worries" about AMD's potential lost income are mis-placed, IMO.

Not to mention Epyc Sales in Enterprise/HPC/Server/cloud/etc are where AMD is positioned to make the "real" money and ALOT of it by all indications. Baidu, Azure and the other rumored/announced
Enterprise/HPC/Server/cloud/etc AMD Epyc clients are further evidence of that.

 

[DrMrLordX]

Ironically it may be the CPU group keeping the GPU group alive with revenues for the next few quarters. Ha! Imagine that.

 

[coercitiv]

Ironically it may be the CPU group keeping the GPU group alive with revenues for the next few quarters. Ha! Imagine that.

The real irony might be RTG selling every GPU they can make in the next few quarters due to the mining craze. Heck, Polaris alone might be able to pay the bills.

 

[coercitiv]

Heck, Polaris alone might be able to pay the bills.

Scratch that, even a Vega FE pays for itself in less than a year.

RTG will sell every GPU they can make.

 

[DrMrLordX]

The real irony might be RTG selling every GPU they can make in the next few quarters due to the mining craze. Heck, Polaris alone might be able to pay the bills.

Well okay there is that. Nvidia and AMD are both going to have some wild times over the next year or two, methinks.

 

[moinmoin]

Moin moin, NUMA unawareness should only cause some inefficiencies due to an additional hop to reach a different socket's or die's physical mem range. Similar to Hypertransport.

And that's what Aenra called the problem 2 to focus on attaining relative performance. To scale and not run into inefficiencies the software needs to be NUMA aware.

 

[wildhorse2k]

And that's what Aenra called the problem 2 to focus on attaining relative performance. To scale and not run into inefficiencies the software needs to be NUMA aware.

In the end yes, but it seems in the meantime if you run into software that is not NUMA aware you will get performance of a single Ryzen 8C (based on performance in Geekbench 4, due to TR having lower clocks and software suffering from inefficiency). This is why I think the best buy will be Threadripper 16C. Threadripper 12C will be just a 6C in worst case, worse than a cheap Ryzen 8C.

 

[Topweasel]

In the end yes, but it seems in the meantime if you run into software that is not NUMA aware you will get performance of a single Ryzen 8C (based on performance in Geekbench 4, due to TR having lower clocks and software suffering from inefficiency). This is why I think the best buy will be Threadripper 16C. Threadripper 12C will be just a 6C in worst case, worse than a cheap Ryzen 8C.

The over exaggerations that happen on this forum is insane sometime. Will a program run better within dies, and inside that inside ccx's. But in no way is non-numa aware programs going to run like an 8 core CPU because of that. There will be some latency issues and even the best programs will struggle in linear growth. The 12 core isn't going to be that much worse. That's what people thought about the 1600x and it is just as fast as it's 8 core clocked counterpoints in programs that use 6 or less heavy threads.

We do not have a good feeling about the actual impact of the latency between CCXs. We don't know the latency between dies. Even if turns out Ryzen's "gaming issues" was ccx related we know business and pro apps even if not Numa aware still managed performance in line with expectations. So let's hold up on the certainties of performance till we actually know what we are talking about.

 

[mattiasnyc]

The die to die communication will be presented as NUMA to the OS, so all software not already NUMA aware won't scale beyond a die anyway (Geekbench is already making quite a mess of this).

Do we know that for sure? I would have thought that a single socket would be shown as one CPU with X cores....?

 

[moinmoin]

Do we know that for sure? I would have thought that a single socket would be shown as one CPU with X cores....?

http://www.anandtech.com/show/11551...7000-series-cpus-launched-and-epyc-analysis/2

https://www.servethehome.com/amd-epyc-7000-series-architecture-overview-non-ce-ee-majors/

 

[wildhorse2k]

The over exaggerations that happen on this forum is insane sometime. Will a program run better within dies, and inside that inside ccx's. But in no way is non-numa aware programs going to run like an 8 core CPU because of that. There will be some latency issues and even the best programs will struggle in linear growth. The 12 core isn't going to be that much worse. That's what people thought about the 1600x and it is just as fast as it's 8 core clocked counterpoints in programs that use 6 or less heavy threads.

We do not have a good feeling about the actual impact of the latency between CCXs. We don't know the latency between dies. Even if turns out Ryzen's "gaming issues" was ccx related we know business and pro apps even if not Numa aware still managed performance in line with expectations. So let's hold up on the certainties of performance till we actually know what we are talking about.

It may be a wild speculation at this point but it is in line with what moinmoin is claiming with NUMA scaling and actual Geekbench 4 results of Threadripper.

 

[ub4ty]

New info drop - (Material Published 7.9.17)
https://www.servethehome.com/amd-ep...ntel-broadwell-ep-qpi-architecture-explained/

Patiently awaiting (Serverthehome) or some other outlet's release of detailed latency/bandwidth/throughput information that details performance numbers for :
> On-die, on CCX
> On-die, intra-CCX
> die-to-die
> Chip to chip

These numbers will be important in further developing Thread-ripper expectations.
Incredible that embargos are lasting this long past actual release and showcase.

 

[ub4ty]

New info drop - (Material Published 7.10.17)

Intel's firing shots at Epyc tomorrow morning bright and early :
NDA ends tomorrow at 9:15 AM PDT
https://videocardz.com/70874/intels-epyc-response-xeon-scalable-processor-skylake-sp

As opposed to AMD, they are using a route/mesh methodology for connecting cores. They are using an updated version of QPI for connecting sockets. Current QPI figures are as follows :
71 ns - CPU cross-QPI/NUMA best case on XEON E5-46*
100 ns - MUTEX lock/unlock 100 ns - own DDR MEMORY reference
135 ns - CPU cross-QPI/NUMA best case on XEON E7-*
202 ns - CPU cross-QPI/NUMA worst case on XEON E7-*
325 ns - CPU cross-QPI/NUMA worst case on XEON E5-46*
Source sauce : https://stackoverflow.com/questions...cost-to-access-various-caches-and-main-memory

For reference, DRAM access times are around 90ns. Thus (IMO), anytime you cross above this in access times, you're in scaled performance territory and need to start doing serious evaluations of your workload's mating with the underlying architecture/micro-architecture.

Exciting times that are near completion.

 

[moinmoin]

AnandTech's own Xeon vs Epyc article also discusses NUMA, calling a 2P Epyc configuration "virtual octal socket":
http://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/2

TR will be a "virtual dual socket" NUMA.

 

[mattiasnyc]

So for those of us (me) that are ignorant: At what point is it triggered so that the OS sees these nodes? Is the OS seeing nodes on Ryzen as well?

 

[ub4ty]

AnandTech's own Xeon vs Epyc article also discusses NUMA, calling a 2P Epyc configuration "virtual octal socket":
http://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/2

TR will be a "virtual dual socket" NUMA.

Excellent. All that needs to be detailed now is the threadripper platform and there will be a complete landscape of offerings.
Very exciting times

 

[mattiasnyc]

I hope that isn't pepe.

 

[Topweasel]

So for those of us (me) that are ignorant: At what point is it triggered so that the OS sees these nodes? Is the OS seeing nodes on Ryzen as well?

It isn't on Ryzen and a strong chance that it won't on TR. The support for 2S on the Servers means you needed Numa no matter what. So honestly I am a little surprised they just didn't node down to CCX. But it makes perfect sense to treat every die as a Numa node if you are going to enable Numa anyways. That doesn't mean they will do that on TR. As a desktop 1S solution setting it to 2 nodes will limit the ability for apps to utilize half the cores.

 

[mattiasnyc]

Well that's what I was thinking, that the OS doesn't see it on Ryzen, which would mean it's not simply a function of a node per CCX. 8 CCX in Epyc I thought explained 8 nodes. But then that'd mean two on Ryzen. And then whatever TR has in terms of total dies (is it 4 or 8?).

Either way, it'll be interesting to see the performance of TR when it appears.

 

[Rngwn]

Well that's what I was thinking, that the OS doesn't see it on Ryzen, which would mean it's not simply a function of a node per CCX. 8 CCX in Epyc I thought explained 8 nodes. But then that'd mean two on Ryzen. And then whatever TR has in terms of total dies (is it 4 or 8?).

Either way, it'll be interesting to see the performance of TR when it appears.

In this screenshot it's not 8 CCX of course, but rather 8 dies in total for this setup since this system is 2S Epyc (pay attention to "2 processors" in the system information). Now looking back to the Ryzen with only one die, that's equals to just 1 NUMA node.

Now the question is, would Windows normally list only 1 NUMA node as the only one "NUMA Node 0" entry too?