The Ryzen "ThreadRipper"... 16 cores of awesome

[IEC]

First Threadripper pre-builts showing up for preorder on Newegg with release date 8/11 listed:
https://www.newegg.com/Product/Product.aspx?Item=N82E16883230259

 

[PeterScott]

Terrible that they would even ship one with 8GB and a spinner boot drive. That won't make for a good experience at all.

It also looks like single channel memory. That should really be odd.

 

[ultimatebob]

Well, you can look for yourself now. ;-) Alienware Threadripper

Heh... I totally called the GeForce 1060 and 8 GB of RAM on the base model. For $3,000, that's pathetic.

 

[scannall]

Could be those extra two are just blanks so they can go down the same line as Epyc.

 

[crashtech]

Could be those extra two are just blanks so they can go down the same line as Epyc.

I was wondering about that, perhaps there are a goodly number of "duds," but if those are exhausted, some kind of spacer or "blank" would have to be utilized. It makes sense that Threadripper would be made on the same assembly line as Epyc, that might be all there is to it.

 

[itsmydamnation]

Remember zepplin dies are cheap ( 20-30USD @ 7k wafer cost depending on yields) and the margin on these processors are huge. So what makes more money just making EPYC packages or making both EPYC and threadripper packages?

 

[PeterScott]

Remember zepplin dies are cheap ( 20-30USD @ 7k wafer cost depending on yields) and the margin on these processors are huge.

Remember from where? I thought these costs were closely guarded secrets.

 

[Rngwn]

I was wondering about that, perhaps there are a goodly number of "duds," but if those are exhausted, some kind of spacer or "blank" would have to be utilized. It makes sense that Threadripper would be made on the same assembly line as Epyc, that might be all there is to it.

My wild guess would be that some of the dies have broken memory/PCIe controller which could very well be considered catastrophic regardless of how many cores would otherwise be non-defective. There are bound to be those kind of dies would it?

 

[maddie]

Remember from where? I thought these costs were closely guarded secrets.

You know the die size, the approx yield and wafer cost. Good luck keeping that secret.

 

[itsmydamnation]

Remember from where? I thought these costs were closely guarded secrets.

its simple math, if AMD are getting charged more then 7k USD for 14nm then they are really getting ripped off

in 2015 http://semiengineering.com/finfet-rollout-slower-than-expected/

At 16nm/14nm, there are 66 mask steps. With an 80% fab utilization rate at 16nm/14nm, the loaded cost is about $4,800 per 300mm wafer, according to Gartner.

50% gross margin = 7200 USD , so its two years later and you would expect WSA lowers cost per wafer for guaranteed throughput / single source.

Then a ~200mm die and look at defects around 0.05 to 0.2 cm sq. This ignores partial failures, built in redundancies or parasitic yield but is the best yard stick we are going to get.
Even people like Arron spink think 7K usd for 14nm wafer is a perfectly reasonable basis to do this kind of evaluation.

 

[PeterScott]

You know the die size, the approx yield and wafer cost. Good luck keeping that secret.

Really, where is yield reported. I searched. This does seem to be quite closely guarded secret.

 

[Yakk]

Really, where is yield reported. I searched. This does seem to be quite closely guarded secret.

80%+ is the general accepted norm for fully functioning 8 core dies.

http://www.guru3d.com/news-story/amd-ryzen-14nm-wafer-yields-pass-80-threadripper-cpus-on-track.html

AMD's costs for Threadripper CPUs must be laughingly low, especially if they figured out how to reuse a portion of their defective dies effectively as it seems they did.

 

[itsmydamnation]

Really, where is yield reported. I searched. This does seem to be quite closely guarded secret.

Samsung reported their defect density for 14nm LLP a year or so ago.
The rumor/internet also said that amd is @ 90% fully functional chips for zepplin.
Then consider that Polars 10 is bigger, has a PCB, 4gb of GDDR5, power regulation and can sell for ( before stupid mining crazy ) $150.

everything points in the one direction, no matter how much you dont want it to ( quick check of your posting history )

 

[Yakk]

80%+ is the general accepted norm for fully functioning 8 core dies.

http://www.guru3d.com/news-story/amd-ryzen-14nm-wafer-yields-pass-80-threadripper-cpus-on-track.html

AMD's costs for Threadripper CPUs must be laughingly low, especially if they figured out how to reuse a portion of their defective dies effectively as it seems they did.

ROTFL!

I have to reply to myself because I never noticed that old Guru3D article actually shows a picture of a delidded Threadripper CPU with 4 CPUs!

AMD THEMSELVES SHOWED IT MONTHS AGO! IT WAS NEVER A SECRET!

ROTFL....

EDIT :

GURU3D old Picture :

 

[beginner99]

My wild guess would be that some of the dies have broken memory/PCIe controller which could very well be considered catastrophic regardless of how many cores would otherwise be non-defective. There are bound to be those kind of dies would it?

Exactly my thought at first. But are there that many dies with this defect?

I also don't think this will change and it's only due to being an ES. If it's 2 dies, why make such a huge socket and IHS?

 

[wildhorse2k]

I would expect all 4 cores to be fully functional, given the high yelds AMD is getting. Maybe TR4 is not that different from SP3 after all.

According to https://www.youtube.com/watch?v=ZoVK6rJR5VE&t=306s some resistors are missing for 2 of the cores. In Epyc pictures it doesn't appear so many are missing. This could be the main difference - 2 dies are simply not powered.

 

[beginner99]

I would expect all 4 cores to be fully functional, given the high yelds AMD is getting. Maybe TR4 is not that different from SP3 after all.

According to https://www.youtube.com/watch?v=ZoVK6rJR5VE&t=306s some resistors are missing for 2 of the cores. In Epyc pictures it doesn't appear so many are missing. This could be the main difference - 2 dies are simply not powered.

Plus the socket is different. So unlocking for sure will not be possible.

 

[wildhorse2k]

Plus the socket is different. So unlocking for sure will not be possible.

I agree it looks like it will be impossible. But since Threadripper and Epyc seem to be the same thing except for one having some missing circuits and another perhaps different AGESA (with OC being locked out), perhaps it would be possible to load AGESA from Threadripper to Epyc and fully unlock it while keeping all 4 dies active. This will be job for BIOS hackers.

 

[PeterScott]

80%+ is the general accepted norm for fully functioning 8 core dies.

http://www.guru3d.com/news-story/amd-ryzen-14nm-wafer-yields-pass-80-threadripper-cpus-on-track.html

AMD's costs for Threadripper CPUs must be laughingly low, especially if they figured out how to reuse a portion of their defective dies effectively as it seems they did.

If their fully functional yields were actually 80%, then they wouldn't change pricing much from scavenging some of the defective 20%.

But this is just pure rumor on the yield, not reporting.

I have to reply to myself because I never noticed that old Guru3D article actually shows a picture of a delidded Threadripper CPU with 4 CPUs!

AMD THEMSELVES SHOWED IT MONTHS AGO! IT WAS NEVER A SECRET!

That was a picture from the Epyc presentation that Guru3D misapplied...

 

[moinmoin]

If it's 2 dies, why make such a huge socket and IHS?

Economy of scale.

Anyway PCWorld claims to have a source tell them that the additional two dies are just "spacers to help maintain the structural integrity of the gigantic heat spreader". http://www.pcworld.com/article/3211...en-threadripper-has-two-mysterious-chips.html

 

[Rngwn]

Exactly my thought at first. But are there that many dies with this defect?

I also don't think this will change and it's only due to being an ES. If it's 2 dies, why make such a huge socket and IHS?

Here is the complete zeppelin die. Outside of the 2 CCXs, there are SerDes and mem controller, each of which is about the size of a Zen core. Assuming the failure is completely random and catastropic, the chances of getting the "dead" dies could be just as common as getting 6 functional cores rather than 8.

But I still don't know about the exact ramifications should the SerDes and mem controller being flawed.

https://en.wikichip.org/wiki/amd/microarchitectures/zen#Die

 

[BigDaveX]

Economy of scale.

Anyway PCWorld claims to have a source tell them that the additional two dies are just "spacers to help maintain the structural integrity of the gigantic heat spreader". http://www.pcworld.com/article/3211...en-threadripper-has-two-mysterious-chips.html

Shame they couldn't have slapped some eDRAM chips in place of the extra two CPU dies, and had them act as an L4 cache for each die.

 

[tamz_msc]

Shame they couldn't have slapped some eDRAM chips in place of the extra two CPU dies, and had them act as an L4 cache for each die.

And where would the EDRAM controller go?

 

[BigDaveX]

And where would the EDRAM controller go?

That was the point I was making; the only way it would work would be if the controller was on-die with the eDRAM and communicated with the CPUs over Infinity Fabric, in which case it'd hardly be any better than going to main memory. A proper controller wouldn't add too much die space, but obviously it's something that would have to be added in Zen's successors.

(Of course, in an ideal world AMD would fill the space with a nice big HBM2 cache, but even if the necessary controller logic was there I shudder to think how much the required interposer would cost)

 

[tamz_msc]

That was the point I was making; the only way it would work would be if the controller was on-die with the eDRAM and communicated with the CPUs over Infinity Fabric, in which case it'd hardly be any better than going to main memory. A proper controller wouldn't add too much die space, but obviously it's something that would have to be added in Zen's successors.

(Of course, in an ideal world AMD would fill the space with a nice big HBM2 cache, but even if the necessary controller logic was there I shudder to think how much the required interposer would cost)

Broadwell-H die.

EDRAM controller is as big as two cores. And it is indeed hardly better than fast DDR4.