Theregister said:
Hopefully this will be some competition in the top end to Intel's server products, I can't imagine how many transistors make up 650+mm^2 on a 22nm process.
Theregister said:http://www.theregister.co.uk/2013/08/27/ibm_power8_server_chip/?page=1
The Power8 chip is implemented in IBM's familiar high-k metal gate processes, which include copper and silicon-on-insulator technologies in a 22-nanometer process. The precise transistor count was not given during the presentation, but the Power8 chip weighs in at 650 square millimetres; this is a bit bigger than Power7+, which used a 32-nanometer process, had 2.1 billion transistors, and a surface area of 567 square millimetres.
The Power8 core has a total of sixteen execution pipes. These include two load store units (LSUs) and a condition register unit (CRU), a branch register unit (BRU), and two instruction fetch units (IFUs). There are two fixed-point units (FXUs), two vector math units (VMXs), a decimal floating unit (DFU), and one cryptographic unit (not labeled in the core diagram above).
Each core now has eight threads implemented using simultaneous multithreading (what IBM calls SMT8), instead of four threads per core with the Power7 and Power7+ chips. And like earlier Power chips, this SMT is dynamically tuneable so a core can have one, two, four, or eight threads fired up.
Each core has 512KB of SRAM memory etched right near it. A segmented NUMA-like L3 cache using what IBM calls a "non-uniform cache architecture" or NUCA for short, spans all twelve cores on the die, for a total of 96MB of L3 cache. That's only 8MB of L3 cache per core, compared to 10MB per core for the Power7+ chip announced last year, but the Power8 has a much more sophisticated main memory subsystem and an L4 cache that obviates the need for so much L3 cache on the die. (More on that in a second.) The L3 cache is implemented using embedded DRAM, as was the case with the Power7 and Power7+ processors.
At a 4GHz clock speed, you can move data into L3 cache from the external L4 cache at 128GB/sec and from the L3 cache out to L4 at 64GB/sec. Data can be crammed into L2 cache from L3 at 128GB/sec (or back out at the same bandwidth). The pipe from L2 cache into the cores has 256GB/sec of bandwidth, but only 64GB/sec in the other direction. Add it all up, across a twelve-core Power8 chip that works out to 4TB/sec of L2 cache bandwidth and 3TB/sec of L3 cache bandwidth.
Hopefully this will be some competition in the top end to Intel's server products, I can't imagine how many transistors make up 650+mm^2 on a 22nm process.
What do you mean by this? The power7+ already is a much faster processor than the top Xeons in server workloads and this announcement will only stretch IBM's lead.
IVB-EX is a game changer, it will have the lead against Power 7+. Power 8 is coming in H2 2014 and is a Haswell-EX competitor.
Are these going to be sold in any systems for less than under $10,000?
Ivy bridge Ex has slipped until at least q1 2014. Power7+ came out in 2012. Power8 is due mid 2014.
Current Power7+ systems start from aorund 6k, so I'd imagine the entry price for Power8 should be similar
http://www-03.ibm.com/systems/power/hardware/710/browse_aix.html
Hopefully this will be some competition in the top end to Intel's server products, I can't imagine how many transistors make up 650+mm^2 on a 22nm process.
Ivy bridge Ex has slipped until at least q1 2014. Power7+ came out in 2012. Power8 is due mid 2014.
Power 7+ came out in H1 2013 or at least its first availability. Paper launch doesn't count. A big lead is expected for IVB-EX over Power 7+. Current plan is H2 2014 for Power 8 and HSW-EX.
Now what we need is Windows ported to Power8, a Visual C++ with cross compilation, some consumer level motherboards, Graphics drivers and we can finally get a decent machine with some progress. Hmm sounds like a lot of work.
"Hopefully" and "some" aren't appropriate words in my opinion: honestly, I'm not into server CPUs but have Intel anything comparable to that beast?
Now what we need is Windows ported to Power8, a Visual C++ with cross compilation, some consumer level motherboards, Graphics drivers and we can finally get a decent machine with some progress. Hmm sounds like a lot of work.
Now what we need is Windows ported to Power8, a Visual C++ with cross compilation, some consumer level motherboards, Graphics drivers and we can finally get a decent machine with some progress. Hmm sounds like a lot of work.
These integrated PCI-Express 3.0 controllers on the Power8 die provide the transport layer for what IBM is calling the Coherence Attach Processor Interface, or CAPI. And this interface will allow accelerators plugged into the PCI bus of a system - possibly GPU coprocessors or field programmable gate arrays - to easily access data and follow pointers in main memory just like processors themselves do.
The PCIe stuff excited me most.
GPGPU accessing main memory and using its pointer structures should be very, very useful. The sooner we get this on x86 the better.
HuMA coming in x86 soon
That thing is a beast!