[Theregister] POWER8 Details revealed

[Idontcare]

I'd imagine if you're making high performance processors, IBM's goals match up pretty well with your own.

Its not just "high performance processors". It is processors with so much leakage current (despite SOI) that they generally are designed with the expectation that they will be water-cooled (in server environment) to keep the temperature low enough that the static leakage power doesn't go sky high.

Not many people can use that type of leaky process tech for air-cooled processors, even if they are going to be plugged into a desktop form factor.

But it is more than that - materials choices are ALWAYS based on what IBM's researchers have already booked the IP for (outside of the CMOS R&D area, meaning TJ Watson Center and so on)

That was the precise cause of the 32nm delay, a BEOL dielectric selection foisted onto the fab club because IBM wanted to go with their internally developed version of the dielectric material because they could build-in licensing requirements for the fab-club members.

(people in this forum probably don't know this, but joining the fab club and paying your dues only gives you access to the process flow itself, but anything used in the process flow - like specific dielectrics and so forth - that are separately developed by other R&D centers within IBM are not "free", IBM further charges its fab club members licensing fees to use those materials in the course of their own internal production fabs)

That's great if IBM's obvious conflict of interest there doesn't come with Achilles heel's in terms of the materials simply not working...but that is precisely what happened at 32nm. The dielectric did not have the mechanical strength necessary after being exposed to the process flow itself such that it could survive the rigors of packaging without resulting in an unacceptably high in-field failure rate.

That decision, made solely by IBM and literally passed down to the fab club members via "edict", set 32nm back nearly 6 months at GloFo as the production engineers in Dresden had to patch and bandaid the process to get it to the point where it was compatible with the delicate nuances of IBM's dielectric.

And the kicker there was once the Dresden engineers fixed the problem, IBM's fab club licensing required GF to disseminate the fix to IBM and all the other fab club members, and yet GF still had/has to pay IBM the licensing dues for using the dielectric still.

Once you have a little real-world "in the trenches" context to put some of the history into perspective it will suddenly start to make sense why GF is putting so much money into their NY fab campus in preparation for separation from the fab club.

There are very few people that have an understanding of that material around here. In addition, the details of many process nodes have not been publicized, so there's not much to compare those numbers to.

For comparison, here's a few of Intel's 22nm numbers:
Contacted gate pitch: as low as 80nm; generally 90nm
M1 pitch: 64nm
SRAM cell: 0.092um²
And a bit more: http://3.bp.blogspot.com/-lI3faVhyf3g/UMd0gfV1gXI/AAAAAAAAATk/QvtIA0ESveU/s1600/Table+1.png

Ironic after all the FUD that was spread about how Intel's 22nm wasn't really a full-fledged 22nm, and here IBM's 22nm design rules are all the less aggressive.

Didn't we just have a few threads about IBM gutting the POWER team. What happened with that?

Power8+ design is done (which is why they can show it off), that IS the time to gut your design team before taking a new direction with the handful of employees you kept

I doubt IBM gutted the design team because they were done with POWER, but they probably felt it was time to clean house and get rid of some dead weight in the transition to forming the team for their N+2 plans.

 

[Homeles]

That decision, made solely by IBM and literally passed down to the fab club members via "edict", set 32nm back nearly 6 months at GloFo as the production engineers in Dresden had to patch and bandaid the process to get it to the point where it was compatible with the delicate nuances of IBM's dielectric.

And the kicker there was once the Dresden engineers fixed the problem, IBM's fab club licensing required GF to disseminate the fix to IBM and all the other fab club members, and yet GF still had/has to pay IBM the licensing dues for using the dielectric still.

Yikes, that really puts things into perspective. I guess I can't give GloFo crap for their 32nm process, now. Well, not too much that is.

Ironic after all the FUD that was spread about how Intel's 22nm wasn't really a full-fledged 22nm, and here IBM's 22nm design rules are all the less aggressive.

I'm just wondering what Intel's secret sauce is for 14nm; it can't be a simple shrink thanks to extra double patterning. Better FinFET design? Improved materials? Sharks with laser beams?

And how will they keep costs down?

 

[Idontcare]

Yikes, that really puts things into perspective. I guess I can't give GloFo crap for their 32nm process, now. Well, not too much that is.

Its actually much worse than any picture I can paint here because I have to be extremely cautious with the specific examples I publicize. These are not just past coworkers of mine who now work on both sides of the fab club aisle, they are also friends, and if I divulge too much then it becomes rather easy for people to divine names (despite my not naming anyone) and the ugliness can get even uglier for everyone

Suffice to say you aren't even seeing the tip of the iceberg :|

I'm just wondering what Intel's secret sauce is for 14nm; it can't be a simple shrink thanks to extra double patterning. Better FinFET design? Improved materials? Sharks with laser beams?

And how will they keep costs down?

I know I am just sounding like a broken record but it really is true that R&D is about "developing lower cost solutions" and not really about "developing technical solutions".

When you see something happen at node N that didn't happen at node N-1, the question to ask is "what did the engineers figure out that finally made feature xyz on node N economically viable versus the cost it represented if it had been implemented at node N-1?"

Why did HKMG get introduced at Intel with 45nm and not 65nm? Was it because HKMG didn't function 2yrs earlier when 65nm was going to production? No, not at all. It functioned, but the cost incurred to create a process flow in production which yielded functioning HKMG transistors was prohibitively expensive.

(we had fully functioning MG xtors at 90nm at TI, but could never get them to be cost-competitive with plain-old SiON on a performance-normalized basis)

Intel's engineers needed an extra 2 yrs of R&D work to lower the cost of manufacturing those HKMG xtors, so they were captured in the 45nm flow instead of the 65m flow.

So when scrutinizing the differences between say 22nm and 14nm, the mindset to have is "the differences (if any) is simply in the cost to implement the feature into production, so the answer to my question must have something to do with cost reduction over time".

Intel's 14nm is going to provide an extra boost above the traditional shrink trendline for successive nodes because of materials selection and taking advantage of things they accepted as tradeoffs at 22nm in limiting the deployment of cost-adders like double-patterning in critical masks.

Why are they doing it at 14nm instead of 22nm? Because it took an extra 2yrs of development for the engineers to find a path to implementing those features into production without blowing up the cost per wafer budget

(And this isn't too say that ALL things are merely a matter of development of cost-reduced means to the same ends, of course some aspects of research are truly held up in the stages of physics and technicalities, but that is not what a CMOS R&D team does when performing node development...the phase of R&D in which truly novel science must be performed is the phase that is referred to as "path finding" or simply "research". R&D is a catch-all acronym but the reality is for most process node R&D teams the work they do is truly just development, sans the research, as they seek ways to integrate pre-existing and already researched building blocks)

 

[SocketF]

Once you have a little real-world "in the trenches" context to put some of the history into perspective it will suddenly start to make sense why GF is putting so much money into their NY fab campus in preparation for separation from the fab club.

Yes it makes totally sense ... thanks for the very interesting insight.
Instead of unfair practices like that, IBM should just go into the fab-business ... then they would be responsible for the customer, also legal responsible.
Maybe also a good decision for AMD to end the SHP-development. In the end its influence on the process was probably zero and if sth goes wrong you cannot blame the responsible party.

Ironic after all the FUD that was spread about how Intel's 22nm wasn't really a full-fledged 22nm, and here IBM's 22nm design rules are all the less aggressive.

Yes, because of rather relaxed parameters for 22nm, I speculate if that process could be similar to a rumored 28SHP process at GF But I cannot find the process specs even of GF's 28nm bulk processes

Anyways, I really wondered, why they didnt use their demoed ETSOI-process .. seems there is something fishy going on again and I wonder if that will also have some implications to STM's FDSOI... I am really more and more worried about FDSOI.

That was the precise cause of the 32nm delay, a BEOL dielectric selection foisted onto the fab club because IBM wanted to go with their internally developed version of the dielectric material because they could build-in licensing requirements for the fab-club members.

Are you talking about the infamous air-gap stuff? Just remembered hearing about it some years ago as the latest and greatest, then it was just silence ...
If you dont want to go into more detail because of your friends and colleagues, it is fine. I am just interested and curious, nothing important for me ;-)

P.S:

Its not just "high performance processors". It is processors with so much leakage current (despite SOI) that they generally are designed with the expectation that they will be water-cooled (in server environment) to keep the temperature low enough that the static leakage power doesn't go sky high.

That explains the latest 200W-Bulldozer edition very well ...

 

[Fox5]

Its not just "high performance processors". It is processors with so much leakage current (despite SOI) that they generally are designed with the expectation that they will be water-cooled (in server environment) to keep the temperature low enough that the static leakage power doesn't go sky high.

So in that case, could we expect AMD processors to gain a greater percentage increase from water cooling than Intel processors?

 

[Homeles]

Yes, because of rather relaxed parameters for 22nm, I speculate if that process could be similar to a rumored 28SHP process at GF But I cannot find the process specs even of GF's 28nm bulk processes

I am extremely doubtful of that, and this is why:
http://www.realworldtech.com/includes/images/articles/iedm10-10.png?b22ba0

With Intel's 32nm node (2nd gen), Intel had an industry leading NMOS drain saturation current of 1620 μa/μm at a Vdd of 1V and leakage current of 100 na/μm, and 1340 μa/um @ 100 na/μm leakage current for PMOS. This is even higher than IBM/GloFo's 32 PDSOI process, with Idsats of 1550 μa/μm @ 100 na/μm and 1220 μa/μm @ 100 na/μm for NMOS and PMOS respectively.

Translation: Intel's 32nm bulk node had higher currents, which is critical for high transistor switching speed, at the same level of leakage as IBM/GloFo's 32nm PDSOI node. Basically, Intel's bulk processes are not only better than everybody else's bulk nodes, but they're even better than their competition's SOI nodes.

Disclaimer: Intel's density is a bit lower (9-14%) than their competition.

Now why does Intel have better performance at the 32nm node? Because they use gate last. This is also the reason why their density isn't as good, despite having the lowest contacted gate pitch in the industry.

Now as far as their 22nm node goes, I believe that Intel has comparable or better density than IBM's 22nm PDSOI node. Although I can't find IBM's SRAM cell size at the moment, Intel's SRAM is as dense as 0.092mm². Their M1 pitch is 64nm vs. IBM's 80nm, and their contacted gate pitch is 90nm (as low as 80nm with special processing) vs. IBM's 100nm. However, I do think IBM's still using gate first, so their gate lengths may be small enough to catch Intel's density.

GloFo will probably have better density than TSMC's 28nm node, but they're not going to win any performance awards. GloFo is using gate first, and TSMC is using gate last. Either way, Intel will have better density.

However, Intel's FinFETs are a mixed blessing. Intel's FinFETs have superior performance over planar transistors at low voltage, up until somewhere around 1.05V. After that, planar transistors have an advantage. This should be true for all multigate FETs: see slide 13. I should point out that those are early numbers, and Intel's tweaked their process since then.

Regardless of this fact, GloFo and TSMC are still a half node behind Intel. GloFo has absolutely no hope of catching Intel's transistor performance with their 28nm node — remember, their performance is undoubtedly behind TSMC's, because they are using gate first, while TSMC is using gate last.

So in short, there simply is no hope of GloFo catching Intel's 22nm with their 28nm process. Both TSMC and GloFo know that the only way to compete with Intel is to roll out 20nm and 16/14nm as fast as possible — coincidentally, this is exactly what they are doing. Intel's 14nm process lands next year, so the clock is ticking (ha, I made a pun).

 

[NostaSeronx]

IBM's SRAM for 22-nm PDSOI is exactly 0.1mm². The FD-SOI/Gate Last group for 20-nm has SRAMs at 0.08mm².

So in short, there simply is no hope of GloFo catching Intel's 22nm with their 28nm process. Both TSMC and GloFo know that the only way to compete with Intel is to roll out 20nm and 16/14nm as fast as possible — coincidentally, this is exactly what they are doing.

20nm and 15nm are actually relatively behind schedule for both TSMC and GlobalFoundries. It is the 10nm that is coming out on time for both of them.

TSMC/GloFo are internally preparing 10nm to hit volume production by 2015.

Cheatsheet:
20-nm Volume -> 2013
15-nm Volume -> 2014
10-nm Volume -> 2015
<-- 4 year gap -->
Graphene

 

[Homeles]

I really hope we get all the juicy details on Intel's 14nm, GloFo's 28nm and 20nm, and TSMC's 20nm processes at IEDM this December.

 

[SocketF]

@Homeless:
Thanks for your contribution, very interesting, but unfortunately a misunderstanding.
I was referring to IBM's process not to intel's.

Because the specs of IBM's 22nm process are so relaxed (less aggressive), I wonder if it could be similar to a rumored SHP28 process of GF. The nanometer-measurements became very blurry, maybe IBM just called it 22nm so they dont look worse than intel.

That process looks roughly just like a direct shrink from 32nm, still gate first, still PD-SOI, just a bit smaller/denser.

 

[Ajay]

IBM's SRAM for 22-nm PDSOI is exactly 0.1mm². The FD-SOI/Gate Last group for 20-nm has SRAMs at 0.08mm².20nm and 15nm are actually relatively behind schedule for both TSMC and GlobalFoundries. It is the 10nm that is coming out on time for both of them.

TSMC/GloFo are internally preparing 10nm to hit volume production by 2015.

Cheatsheet:
20-nm Volume -> 2013
15-nm Volume -> 2014
10-nm Volume -> 2015
<-- 4 year gap -->
Graphene

What??

Intel won't have 10nm online till sometime in 2015, the are concerns CPU introduction won't be till 2016. Oregon DX1 Mod_2, I believe, is looking to ramp up first - probably quad patterning since 450mm wafers need an ~1kW light source. I don't see EUV reaching that output anytime soon, or at least not without it's own attached SMR. 450mm wafers will offset the per die cost of quad patten exposure. I don't see how any other foundry is going to move to 10nm economically without either a 450mm wafer process capability or an unexpected breakthrough with EUV on 300mm wafers.