Just like AMD's professional video card lines (FireGL and compute cards), it's a way more profitable market per sale. Ideally, you get scale by selling your stuff for whatever you can on the consumer market, and then reap the benefits on the highly profitable professional market.
Plus, AMD had some good advantages in the server market until Nehalem, and was even pretty competitive up until bulldozer.
That said, I think more focus on the consumer market would have benefited them greatly, even if it was just with more appropriate product placement.
IE: Focus on low power designs for laptops and ultraportables, and claim that highly profitable segment from Intel. AMD never put much effort into low power designs, even when they've had good power efficiency.
Instead of Phenom being a quad core, it should have been a native dual core design similar to the core 2 duo and with no L3 cache. In many real world situations, they probably could have had equal to or better performance than what they offered, but with vastly lower costs per chip.
Really, AMD shouldn't have launched consumer lines with L3 cache at all (at least not on the low end), it bloats die size to a large amount and AMD's designs still under perform.
Instead of bulldozer, a die shrunk and up-clocked Phenom II based design would have been better. A Bulldozer module is nearly 2x the size of a Phenom II core, ie, their innovative design doesn't seem to have saved them very much die space.
Clearly modules aren't great for peak performance, but for perf/watt they are the way to go. The idea behind the module configuration is to achieve very high resource utilization.
I'm hoping that they improve on the caches in Vishera (wouldn't be surprising, given that it will be based off of server designs), and then for steamroller improve the frontend.
I think you're spot on.
I really havn't understood the whole L3 decision by either intel or AMD.
The yorkfields had 12MB of fast L2 which gave them incredible performance characteristics.
Maybe i'm missing something, but why do we need/want L3 again ?
Yorkfield was not fast at all for synchronizing between threads on both chips. And its 6+6 MB cache was a waste due to having duplicate data in both halves. Nehalem's monolithic L3 cache is superior, despite being "only" 8 MB. It also uses more power efficient 8T cells. Furthermore, Nehalem's L2 cache latency (11 cycles) is lower than that of Penryn/Yorkfield (18 cycles). And even though it's smaller and thus there are more misses, the L3 cache and integrated memory controller makes it all result in a lower average access lantecy.I really havn't understood the whole L3 decision by either intel or AMD.
The yorkfields had 12MB of fast L2 which gave them incredible performance characteristics.
Maybe i'm missing something, but why do we need/want L3 again ?
There are rumors that Haswell might even include an L4 cache consisting of eDRAM. This would allow the expensive SRAM caches to be smaller while saving power by going off-package less often.
intel's L3 is more like a protection... if L2 cache misses data, the CPU will find the missing data it at L3.
for amd....i don't really remember
Just wondering what is L4 cache?
A 4th level cache? Its as such no different than L1, L2 and L3.
Wouldn't it be slower since ever level of cache get slower than the previous one.
One common task in the future will be to work on streamed data, usually not fitting into any cache. In such cases, only prefetching helps lowering average latencies, but throughput wouldn't increase (as it would when repeatedly using cached data).But it would still be faster than main memory.
The only reason we got L3 is due to the fact, that sharing the L2 with so many cores would make it too slow. The L4 is currently still a rumour and I guess it will stay so. But if we get an L4. It would be due to the above reason.
these are really bad names. Bulldozer, steamroller,... very large, very heavy, and very slow vehicles. Not what I want in my CPU.
That's why I'm especially skeptical. A local memory, or cache just for certain uses (make it exclusive where it would need to be CC, and the rest of cache management is made easier), would not terribly affect the rest of memory speeds. A huge L4, OTOH, added to L3 (if it's a local memory, or non-CPU-core cache, it's not really L4, is it?), would require very big cache lines, sequential cacheline extents, or some other method of keeping CAM lookups quick (but which could affect the hit rate negatively), or could add substantial time to lookups. Memory may be slow, but slower cache is not ideal, either. There is definitely a point at which making them faster for the sake of keeping the CPU busy when every request is a hit is worth it over making them bigger to reduce the need to go out to RAM on misses.Wouldn't it be slower since every level of cache get slower than the previous one.
Yes and dedicated 4x1MB L2 caches (without L3) wont be able to share data at all.As ShintaiDK already wrote, a dedicated L2 cache was needed because sharing the L2 cache between 4 cores will be slow.
The L3 cache acts as the center of memory coherency of the whole CPU. With that, intel could use also the less complex MESIF protocol.- to efficiently probe cores on other sockets
AFAIK it was just introduced with the first six core CPUs, i.e. Istanbul, not Shanghai.Note: to efficiently proble cores on different sockets, Shangai and Bulldozer based chips include a "snoop filter" features.
No. Have you not read this article? http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/1Guys I've really gotta say that Steamroller is going to be really bad. It's still based off the original Bulldozer design. There's only so much they can do with this thing. It's just like the P4.
It was probably to save die space. AMD could use some increased associativity to counter the resources being shared and small cache size.does anyone else think that the small L1 caches on bulldozer could be killing performance ?
per core (half module) there is 1/2 the instruction and 1/4 the data compared to stars (correct me if i'm wrong).
Granted the instruction cache is shared, but even then it must feed 2 threads.
Was there any justification for decimating the L1 cache sizes other than saving die space ?
Have they sufficiently compensated (if possible) ?
Apart from your benefits' list, I would also mentioned the increased robustness against bad OS schedulers. If the operating system has a bad scheduling algorithm, then it does not matter much for a modern intel CPU. The cached data is still preserved in the L3. A thread which is scheduled to run on another core can load the data from L3,i.e. the caches are always hot. However, this is impossible on an AMD CPU, data has to be loaded from memory in that case, because the L3 does contain different data compared to the L2 (only exception would be a thread, changing clusters within one Bulldozer-module).
I double-checked and yes, you are right: it was introduced with Instanbul core: http://www.anandtech.com/show/2774/2AFAIK it was just introduced with the first six core CPUs, i.e. Istanbul, not Shanghai.
Furthermore, here we see again the pros and cons of intel's decision for a small L2. Yes, AMD has the bigger, usable cache setup, but for multi-processor systems, AMD *also* has to cut down the usable cache-size.
Theoretically, that is the better way, because the 1P / desktop users do not have to suffer from the server-architecture-penalty, i.e. AMD user have the choice to sacrifice L3-cache size for a better MP scalability. Intel users do not have that choice. However, in reality, intel CPUs are still faster, due to other factors. Furthermore, since the 32nm generation, intel's L3 caches run at full core-clock speed, thus acting more like a "L2.5" cache. What I want to point out with that strange notation is the fact that intel's L3-cache of its 32/22nm CPUs is (nearly) as fast as AMD's L2 caches of Bulldozer.
Well let's wait and see if AMD will change something in the cache setup for Steamroller. I won't hold my breath, though.