does anyone else think that the small L1 caches on bulldozer could be killing performance ?
per core (half module) there is 1/2 the instruction and 1/4 the data compared to stars (correct me if i'm wrong).
Granted the instruction cache is shared, but even then it must feed 2 threads.
Was there any justification for decimating the L1 cache sizes other than saving die space ?
Have they sufficiently compensated (if possible) ?
Looking at These benchmarks comparing bulldozer with a 200MHz clock advantage against x6. Not only are the L1 cache sizes smaller, but the overrall latency and bandwidth of both L1 and L2 are worse.
No. Have you not read this article? http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/1
Bulldozer's definitely a great concept, but it's got some glaring flaws. Piledriver will make some significant strides towards hammering those out. AMD can only do so much on the 32nm node though. It appears Bulldozer wasn't really ready for 32nm, as there isn't much room for improvement (literally).
The clocks for the APUs (Trinity) are already official:What do you think the clock speed, turbo, and max turbo will be of the flagship steamroller cpu? I'm almost positive the flagship piledriver will be 4.2ghz with 4.7ghz turbo core
Yes - clock speed. For example the L2 has a latency of 18 cycles, if it has a size of1MB, and 20 if it is 2MB. Less cache is accessed faster. However, I still wonder why they have kept a 4 cycle latency for the little 16kB L1. Intel has 4 cycles to, but they have a 32kB 8way write-back design, i.e. much more complex. Well, I guess they have their reasons.does anyone else think that the small L1 caches on bulldozer could be killing performance ?
Was there any justification for decimating the L1 cache sizes other than saving die space ? Have they sufficiently compensated (if possible) ?
It was probably to save die space. AMD could use some increased associativity to counter the resources being shared and small cache size.
P4's problem was that intel didn't foresee the steep increasing leakage problem. AMD's engineers however, had that in mind. Now, if you want to tell us some inside story, please feel free to enlighten us with the technical details. Statements without the "because"-part, however, are useless and merely babbling.So was the P4. Failure for both? Cant clock high enough.
Bulldozer uarch is unfixable.
I have red about it, but I am still very skeptical. If I run for example the cinebench single thread benchmark and I check the task-manager, then I have ~13% CPU utilization spread evenly across *all* my 8 cores. I thought that it maybe due to my Win2008R2 Server OS, but it seems it seems it is a problem for normal W7, too, there are several people complaining about the core parking feature:This is true, but modern operating systems tend to don't move threads between cores without a very good reason: http://www.tomshardware.com/reviews/intel-core-i5,2410-8.html
With Windows Vista it was a major concern for AMD Phenom CPU, as you correcly noted.
Oh yes, scheduling is veery complex. I red a few articles about the Linux and BSD schedulers, and there is really lots of work going on. However, it seems that Linux has chosen to implement one dedicated run queue per core, whereas windows has imo 1 global run queue, hence the core hopping ( I didnt find sources for windows, but seeing the threads hopping around, I assume it is only 1 run queue). I wonder if something will change in Win8. At least this will bring the "true" bulldozer scheduler. The current patches for Win7 are imo just re-using the features implemented for Intel's hyperthreading.A Bulldozer-specific problem that remain with the new W7 patch also, is that ideal thread schedule heavily depend on the expected instruciton mix and others difficult to predict factors. For example, FP-heavy threads should be scheduled on a different modules (this maximize FPUs usage), while integer thread can be scheduled both on different modules (when they don't share data) or on the same module (when they share data, for let Turbo boost to aggressively kick in and use the L2 to quicky pass data between the two cores).
So, the ideal scheduling on Bulldozer-class cores is a quite complex affair, and often the OS scheduler simply don't has enought information to do the best choice.
Doh, I was too lazy to write "sandy-bridge" and decided to go with the shorter 32nm, and look what happened, it got wrong. You are right, of courseIf I remember correctly, the first Intel 32nm product, westmere, had L2 cache that didn't run at core clock. It is with Sandy Bridge that L2 runs at core clock
I have red about it, but I am still very skeptical. If I run for example the cinebench single thread benchmark and I check the task-manager, then I have ~13% CPU utilization spread evenly across *all* my 8 cores. I thought that it maybe due to my Win2008R2 Server OS, but it seems it seems it is a problem for normal W7, too, there are several people complaining about the core parking feature:
http://bitsum.com/about_cpu_core_parking.php
However, it seems to be disabled for Bulldozer CPUs with one of the scheduler hotfixes:
http://support.microsoft.com/kb/2646060/en-us
Oh yes, scheduling is veery complex. I red a few articles about the Linux and BSD schedulers, and there is really lots of work going on. However, it seems that Linux has chosen to implement one dedicated run queue per core, whereas windows has imo 1 global run queue, hence the core hopping ( I didnt find sources for windows, but seeing the threads hopping around, I assume it is only 1 run queue). I wonder if something will change in Win8. At least this will bring the "true" bulldozer scheduler. The current patches for Win7 are imo just re-using the features implemented for Intel's hyperthreading.
Doh, I was too lazy to write "sandy-bridge" and decided to go with the shorter 32nm, and look what happened, it got wrong. You are right, of course
regards
SF
Bulldozer's pipeline is only slightly larger than Sandy Bridge's. You have absolutely no credibility to be making calls like that.So was the P4. Failure for both? Cant clock high enough.
Bulldozer uarch is unfixable.
Bulldozer's pipeline is only slightly larger than Sandy Bridge's. You have absolutely no credibility to be making calls like that.
Bulldozer's pipeline is only slightly larger than Sandy Bridge's. You have absolutely no credibility to be making calls like that.
He's probably referring to this: http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2Interesting considering none of the 2 companies have disclosed the pipeline length. So can you show me where that information is published?
Personally I would guess that SB got around 16 stages and Bulldozer around 25 stages. Misprediction latency gives an estimate that its around 50% longer than Phenom II.
Then you should have stated your point. We've only seen thorough benchmarks for one generation of Bulldozer. You cannot say the architecture is a failure solely based off of its first implementation. By your logic, I could say that Intel's current desktop uarch is doomed because the P6 architecture (which Conroe, Nehalem and Sandy Bridge are derived from) was a flop at the time of its introduction. And it was.Interesting considering none of the 2 companies have disclosed the pipeline length. So can you show me where that information is published?
Personally I would guess that SB got around 18 stages and Bulldozer above 25 stages.
My point was rather that Bulldozer uarch is based on a INT cores that only got 2 issue ports and the focus on simple instructions.
I could have sworn i read Bulldozer's pipeline is on par with Netburst's
Then you should have stated your point. We've only seen thorough benchmarks for one generation of Bulldozer. You cannot say the architecture is a failure solely based off of its first implementation. By your logic, I could say that Intel's current desktop uarch is doomed because the P6 architecture (which Conroe, Nehalem and Sandy Bridge are derived from) was a flop at the time of its introduction. And it was.
I thought we had seen 2 generations:
http://www.anandtech.com/show/5831/amd-trinity-review-a10-4600m-a-new-hope
I worded that specifically to imply that Piledriver hasn't seen thorough benchmarks yet. Mobile benches are too "muddy." Regardless, we haven't seen it run at desktop TDPs.We've only seen thorough benchmarks for one generation of Bulldozer.
I could have sworn i read Bulldozer's pipeline is on par with Netburst's
Interesting. I should try with my Arrandale-based notebook...
Personally I would guess that SB got around 16 stages and Bulldozer around 25 stages. Misprediction latency gives an estimate that its around 50% longer than Phenom II.
They have...I guess Its just like the term pipeline length has been kind of abandoned by them for which in modern CPU varies from different application.Interesting considering none of the 2 companies have disclosed the pipeline length. So can you show me where that information is published?.
They have...I guess Its just like the term pipeline length has been kind of abandoned by them for which in modern CPU varies from different application.