Translation from linear address space to physical address space when paging is turned off

[chrstrbrts]

Hello,

OK, in modern 64-bit Intel systems, processors, while in the 64-bit sub-mode of the IA-32e mode (I suppose what most people just call 64-bit mode), have a linear address space of 2^64 bytes.

Now, current computers can't reach all 2^64 addresses, but I think that they use the bottom 2^48.

That is, the theoretical linear address space is 0 to (2^64) - 1, but the actual current linear address space is 0 to (2^48) - 1.

But, 2^48 is still a huge number, 281,474,976,710,656 to be exact; that's over 281 trillion.

Now, computers don't come with anything close to that amount of RAM (NSA hardware excluded).

Further, if I have paging turned off and can't rely on swapping out with a non-volatile memory device to extend the physical address space, then linear addresses directly become physical addresses with no further manipulation.

So, what happens if my 64-bit computer running in 64-bit mode with paging turned off has 6 GB of RAM, but a process that's running upon it puts 7,000,000,000 (7 billion in decimal) or something greater but less than (2^48) - 1 on the address bus in an attempt to read or write or execute?

Obviously, 7,000,000,000 > 6 binary billion.

Thanks.

 

[chrstrbrts]

Uh.....anyone?

Exdeath, you onine?

 

[Ken g6]

Further, if I have paging turned off and can't rely on swapping out with a non-volatile memory device to extend the physical address space, then linear addresses directly become physical addresses with no further manipulation.

I'm not sure that's a correct assumption. I think the pages are still there; they're just not swapped to "a non-volatile memory device"

So, what happens if my 64-bit computer running in 64-bit mode with paging turned off has 6 GB of RAM, but a process that's running upon it puts 7,000,000,000 (7 billion in decimal) or something greater but less than (2^48) - 1 on the address bus in an attempt to read or write or execute?

If that range isn't allocated, "Segmentation fault (core dumped)". If you've somehow managed to allocate that range (e.g. with Linux, it doesn't really create some allocations until they're used), you might be able to have a page with that address and not have pages with lower addresses. But that's very hypothetical.

 

[uclabachelor]

Hello,

OK, in modern 64-bit Intel systems, processors, while in the 64-bit sub-mode of the IA-32e mode (I suppose what most people just call 64-bit mode), have a linear address space of 2^64 bytes.

Now, current computers can't reach all 2^64 addresses, but I think that they use the bottom 2^48.

That is, the theoretical linear address space is 0 to (2^64) - 1, but the actual current linear address space is 0 to (2^48) - 1.

But, 2^48 is still a huge number, 281,474,976,710,656 to be exact; that's over 281 trillion.

Now, computers don't come with anything close to that amount of RAM (NSA hardware excluded).

Further, if I have paging turned off and can't rely on swapping out with a non-volatile memory device to extend the physical address space, then linear addresses directly become physical addresses with no further manipulation.

So, what happens if my 64-bit computer running in 64-bit mode with paging turned off has 6 GB of RAM, but a process that's running upon it puts 7,000,000,000 (7 billion in decimal) or something greater but less than (2^48) - 1 on the address bus in an attempt to read or write or execute?

Obviously, 7,000,000,000 > 6 binary billion.

Thanks.

A 64-bit bus will always be physically connected (ie, linearly addressed) to each byte of the 6GB of ram. This is true in any system as long as the physical address you're trying to reach is less than the system bus width (ie, 64-bit).

When you get past the physical hardware, you have to deal with registers that set the memory map of the address space - so even if let's say 4GB of memory is physically connected to address bits 0-23 on hardware, you can map that memory space to any region within 2^64 by setting the registers with the proper values.

Anything that happens after that is all OS based and if you access a bad memory region then you have bad things happen.

 

[chrstrbrts]

I'm not sure that's a correct assumption. I think the pages are still there; they're just not swapped to "a non-volatile memory device"

Well, I got that from Intel's manual; that's how they explained it.

If that range isn't allocated, "Segmentation fault (core dumped)". If you've somehow managed to allocate that range (e.g. with Linux, it doesn't really create some allocations until they're used), you might be able to have a page with that address and not have pages with lower addresses. But that's very hypothetical.

The assumption is that paging is turned off.

I know that you think that turning paging off just turns the swapping aspect off and that you can still take a linear address and send it to some page that occupies some totally different place in physical memory e.g. linear address 100 is mapped to a page that runs from physical address 10 to 65, but that is not what the Intel manual says.

The manual I have is recent (published in June 2016), and it makes it quite clear, through both text and diagram, that when paging is turned off, linear addresses become physical addresses straight away.

Though, your answer about segmentation fault seems reasonable.

A 64-bit bus will always be physically connected (ie, linearly addressed) to each byte of the 6GB of ram. This is true in any system as long as the physical address you're trying to reach is less than the system bus width (ie, 64-bit).

This confuses me.

How?

If I put address 10,000,000,000 on the bus and I only have 6 binary billion bytes of RAM then what happens?

How does the memory controller/RAM controller handle an address outside the range of available physical RAM?

That's my question.

When you get past the physical hardware, you have to deal with registers that set the memory map of the address space - so even if let's say 4GB of memory is physically connected to address bits 0-23 on hardware,

Do you mean address bits 0-31?

Otherwise, I have no idea what you mean.

you can map that memory space to any region within 2^64 by setting the registers with the proper values.

WHAT?!

Nothing even remotely similar to this has been mentioned in Intel's manual.

Where are these special memory mapping registers?

Surely not on the processor.

On the memory controller, perhaps?

I appreciate your response, but can you explain further please?

 

[exdeath]

Assuming segment descriptor in long mode is base 0 limit 2^64-1 and no paging , and depending on the mother board, youd wrap, mirror, or the external logic would flag a bus error IRQ or something. Who knows

Most likely it would just truncate the upper 16 bits and wrap and then it's up to the mother board logic how it responds to the 2^48-1 physical address range.

As for mapping things at the physical level without paging you interact with the programmable IO registers on the chip set. This is how you map PCI video memory wherever you want, etc.

 

[chrstrbrts]

As for mapping things at the physical level without paging you interact with the programmable IO registers on the chip set. This is how you map PCI video memory wherever you want, etc.

As I suspected.

These registers aren't processor registers; they exist on the chipset somewhere outside of the processor.

 

[exdeath]

As I suspected.

These registers aren't processor registers; they exist on the chipset somewhere outside of the processor.

You can program the logic on the system board to establish the physical memory map (eg map the PCI to respond to 0xE0000000-EFFFFFFF) to map video RAM for example. 0xE0000000 for the CPU is 0x00000000 to the GPU the first byte of VRAM. This is controlling the programmable address decode and chip select and arbitration logic on the system board to respond to physical external address pins. (It's more transaction and packet based now behind the scenes but keeping it simple).

Applications still do not see this however if there are no page table entries referencing those physical blocks. Actually the OS didn't see them either if it doesn't want to because the OS memory map is virtualized by page tables too.

Then you call DirectX Lock to return a pointer to a surface and this invokes a syscall which causes the OS to say put physical address index where the E0007000 physical page frame is in your page tables to appear to the application to be at 70001000 (or gives you a temp RAM buffer then copies it when you unlock). When you wrote to 70001000 that data actually left the CPU pins after translation to physical address E0007000 which the mother board and bus controller logic responds to and ultimately it ends up sitting in video memory @ 0x00007000.

Hence the term "Direct" X , it was a API that arose due to the need for high performance to have "direct" hardware access which was taken away with the move from DOS to Windows.

 

[chrstrbrts]

You can program the logic on the system board to establish the physical memory map (eg map the PCI to respond to 0xE0000000-EFFFFFFF) to map video RAM for example. 0xE0000000 for the CPU is 0x00000000 to the GPU the first byte of VRAM. This is controlling the programmable address decode and chip select and arbitration logic on the system board to respond to physical external address pins. (It's more transaction and packet based now behind the scenes but keeping it simple).

Applications still do not see this however if there are no page table entries referencing those physical blocks. Actually the OS didn't see them either if it doesn't want to because the OS memory map is virtualized by page tables too.

Then you call DirectX Lock to return a pointer to a surface and this invokes a syscall which causes the OS to say put physical address index where the E0007000 physical page frame is in your page tables to appear to the application to be at 70001000 (or gives you a temp RAM buffer then copies it when you unlock). When you wrote to 70001000 that data actually left the CPU pins after translation to physical address E0007000 which the mother board and bus controller logic responds to and ultimately it ends up sitting in video memory @ 0x00007000.

Hence the term "Direct" X , it was a API that arose due to the need for high performance to have "direct" hardware access which was taken away with the move from DOS to Windows.

I'm looking forward to learning all I can about the graphics subsystem.

In good time, of course.