- Dec 25, 2013
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TSMC Symposium: 10nm is Ready for Design Starts at This Moment
TSMC Symposium: New Low-Power Process, Expanded R&D Will Drive Vast Innovation: TSMC Executive
Moores Law Not Slowing DownTSMC Executive
The good news is that scaling still works. Due to aggressive scaling, the 10nm FinFET (10FF) process node increases logic density by 2.1X compared to the TSMC 16nm FinFET Plus (16FF+) process node. Compared to 16FF+, the 10FF node can offer a 20% speed increase at the same power, or more than 40% power reduction at the same speed. TSMC has demonstrated a fully functional 256Mb SRAM in 10FF technology with die size scaling close to 50% of 16FF+.
New features in 10FF include a unidirectional (1D) layout style and new local interconnect layer. These features help 10FF achieve a 2.1X logic density improvement over 16FF+, whereas normally TSMC gets about a 1.9X density boost for node migration, Woo said. In addition to the density improvement, the 1D Mx architecture can reduce CD (critical dimension) variation by 60%, she said.
Also:10FF requires double patterning, but TSMC does not use not the relatively simple litho-etch, litho-etch patterning that is used at 20nm and 16nm. The problem with LELE, Woo said, is that overlay changes can result in variation in the line space. While this is tolerable in 20nm and 16nm, at 10nm this variation will translate into a very small metal space. That can result in an immature dielectric breakdown. Thus, TSMC 10FF uses a self-aligned spacer process that assures that uniform metal line spacings are maintained.
Another 10nm challenge is that resistance goes up significantly as metal layers scale down. Selectively relaxing the metal pitch provides a way to optimize performance versus density. 10FF allows the designer to make this kind of adjustment in order to find the best tradeoff.
TSMC Symposium: New Low-Power Process, Expanded R&D Will Drive Vast Innovation: TSMC Executive
Moores Law Not Slowing DownTSMC Executive