I think by now it's clear, the node name each foundry uses is decided by marketing not engineering. With that said, what's the performance characteristics and implications. Consider this, the actual processor cores take very little space on the SoC even using 16FFC. The elephant in the room is the logic board and replacing the substrate with wafer level integration is far more of a story than going to 7nm. So, my only interest in 10nm and 7nm would be the the performance/power ratio improvements at each node, not the actual density.
I'd like to see a chart comparing that between each foundry's node.
I don't think this ("the node name each foundry uses is decided by marketing not engineering") is completely true. I have suggested, for example, that fin width can be considered as *somewhat* tracking the node number. I've reason to believe this is correct, but it's hard to be sure.
Intel 14nm fins are 8nm wide. I have never seen numbers for the width of anyone else's fins.
I suspect that the reason companies are so happy to release the sorts of numbers that are being quoted in this thread is precisely that they are not especially useful. The numbers that likely DO matter the most (among which, I suspect, are fin width) are the numbers that we never see quoted. (Or are quoted for the research version, not the manufacturing version, or are quoted three years after the manufacturing process was introduced.)
But I do agree with the larger point --- there are few purposes these days for which density is vastly interesting. Tweaks to the process (the upcoming tweaks appear to SiGe and III-V modifications to the transistors, and maybe air gaps for TSMC --- Intel already has them, and I assume IBM will demand them), and packaging seem more significant issues to track for the purposes of interest to most of us.