witeken
Diamond Member
- Dec 25, 2013
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If SRAM size will be basically the same, you wouldn't expect major differences, would you? I don't in any case.Is this for SRAM density, logic density, or both?
So if SRAM size is determined by gate pitch and fin pitch, that would explain the 0.54x scaling at Intel 14nm: 0.78*0.7 (unless that's just a coincidence). Given that gate pitch again scales 0.77x, that implies that if they shrink again (at least) 0.54x, then fin pitch will be a most 29-30nm.SRAM density is mainly determined by CGP (Contacted Gate Pitch) in one direction and isolation pitch in the other direction. MP (Metal Pitch) is usually not a limiting factor because an SRAM column only needs four metal lines: Vdd, Vss, BL, and BLB. (BL: Bit Line, BLB: Bit Line Bar/Complement) Furthermore, in a FinFET manufacturing technology the choice of fin pitch entangles the metal and isolation pitch together.
On the other hand, logic density to the first order is determined by CGP × MP. As such, metal and isolation pitch can be adjusted independently to meet the logic and SRAM density targets.
Curiously, neither the foundry nor the IDM has disclosed its metal pitch yet.
Ok..Sorry missed your post before, seems people are just criticizing my link without explaining what is wrong with it.
OK.My understanding about transistors are not so deep but I'm open why it is wrong.
What's wrong with it? First, the dates. If a node is released at the end of the year, it looks much better, etc. So it should be more precise with a year divded in quarters. But, even then, the dates are just forecasts. They could and probably will change in one or another direction. And bseides, in an article one should always produce graphs from tables. Tables are raw data. But anyway..
But even if you ignore the table that is divded in years, the thing that is wrong most of all with it is the formula.
Standard Node = 0.14 x (CPHP x MMHP)^0.67
I will not go into all the mathematical details, but the formula is really, really, really wrong in a very big way. The thing that messes it all up is the ^0.67 power. The power should have been 0.707, that is the only correct value (1/1sqrt(2)). So what will happen is that this formula will make differences look bigger because 0.67² is 0.45, which is not the correct 0.5 scaling.
But using a flawed formula is not even everything, the data (for the 10nm and 7nm and 5nm nodes because those have not been published) that was put in is also dead wrong and completely fictitious. You can decompose -- reverse engineer -- the formula to see what numbers where put in. So if you do the math, you will see that this table projects following:
For TSMC, things look reasonable:
16nm = 1441 (= 5764 nm²)
10nm = 701 (= 2804 nm²) --> 2.1x (well, I would rather put my money on 1.92x, but TSMC has publicly said both numbers)
7nm = 435 (= 1740 nm²) --> 1.6x (seems right)
5nm = 220 (= 880 nm²) --> 1.98x (so here because there is completely no data from TSMC about what it will do at 5nm, the author just assumed that it would shrink 2x and put that in the formula)
Now, for Intel, things are aweful.
14nm = 909 (= 3.636 nm²) --> which is completely correct (but don't now go to the table and cut off everything to the right of 14nm, because remember the formula will still skew things up)
10nm = 542 (= 2.168 nm²) --> 1.68x (which is completely wrong because Intel will shrink by about 2.00x, about the same as 14nm, so it's not even close)
7nm = 322 (= 1.288 nm²) --> 1.68x (again 1.68x, you can clearly see that these numbers were just invented out of thin air; but it are lies, because when Intel does a shrink, it is around 2x, they take their time for a real full node shrink)
So, these are the raw numbers that were put in the formula. The thing that comes out of the formula, however, has gone through that horrible 0.67 numbers, which makes TSMC's bigger scaling that was put as raw number look even better -- the number that comes out for TSMC, the number you see in the table is both favored by the data that was put in, and by the formula.
So basically, what is done here is that someone used a formula that's already mathematically wrong to put in their secret numbers that are in favor of TSMC, so they can make a reliable looking table with that and claim that this is how things will be, while in fact it could not have been more wrong.
This is the ultimate misleading of course, if you fudge the data and make sure it's almost impossible to find out unless you have someone with some knowledge who decides that it might not be a bad idea to reverse engineer the stuff...
TSMC has only disclosed 2 significant figures: the 2 and the 7. It could be anywhere from 0.0265µm² to 0.0274µm².But in your post before you say Tsmc 7nm (0.027µm²) > Intel 10 nm (0.0272µm²). So even you predict Tsmc take leadership in 2018.
If you have even a little bit of knowledge of mathematics and rounding, you should see that my Intel estimate (still an estimate based on 22->24) rounds to the same 0.027µm². And in any case, those 2 numbers are within 0.8% of each other, so using anything but the = sign is crazy.
What does this 'a' mean?