TSMC 7nm info

[witeken]

Is this for SRAM density, logic density, or both?

If SRAM size will be basically the same, you wouldn't expect major differences, would you? I don't in any case.

SRAM density is mainly determined by CGP (Contacted Gate Pitch) in one direction and isolation pitch in the other direction. MP (Metal Pitch) is usually not a limiting factor because an SRAM column only needs four metal lines: Vdd, Vss, BL, and BLB. (BL: Bit Line, BLB: Bit Line Bar/Complement) Furthermore, in a FinFET manufacturing technology the choice of fin pitch entangles the metal and isolation pitch together.

On the other hand, logic density to the first order is determined by CGP × MP. As such, metal and isolation pitch can be adjusted independently to meet the logic and SRAM density targets.

Curiously, neither the foundry nor the IDM has disclosed its metal pitch yet.

So if SRAM size is determined by gate pitch and fin pitch, that would explain the 0.54x scaling at Intel 14nm: 0.78*0.7 (unless that's just a coincidence). Given that gate pitch again scales 0.77x, that implies that if they shrink again (at least) 0.54x, then fin pitch will be a most 29-30nm.

Sorry missed your post before, seems people are just criticizing my link without explaining what is wrong with it.

Ok..

My understanding about transistors are not so deep but I'm open why it is wrong.

OK.

What's wrong with it? First, the dates. If a node is released at the end of the year, it looks much better, etc. So it should be more precise with a year divded in quarters. But, even then, the dates are just forecasts. They could and probably will change in one or another direction. And bseides, in an article one should always produce graphs from tables. Tables are raw data. But anyway..

But even if you ignore the table that is divded in years, the thing that is wrong most of all with it is the formula.

Standard Node = 0.14 x (CPHP x MMHP)^0.67

I will not go into all the mathematical details, but the formula is really, really, really wrong in a very big way. The thing that messes it all up is the ^0.67 power. The power should have been 0.707, that is the only correct value (1/1sqrt(2)). So what will happen is that this formula will make differences look bigger because 0.67² is 0.45, which is not the correct 0.5 scaling.

But using a flawed formula is not even everything, the data (for the 10nm and 7nm and 5nm nodes because those have not been published) that was put in is also dead wrong and completely fictitious. You can decompose -- reverse engineer -- the formula to see what numbers where put in. So if you do the math, you will see that this table projects following:

For TSMC, things look reasonable:

16nm = 1441 (= 5764 nm²)
10nm = 701 (= 2804 nm²) --> 2.1x (well, I would rather put my money on 1.92x, but TSMC has publicly said both numbers)
7nm = 435 (= 1740 nm²) --> 1.6x (seems right)
5nm = 220 (= 880 nm²) --> 1.98x (so here because there is completely no data from TSMC about what it will do at 5nm, the author just assumed that it would shrink 2x and put that in the formula)

Now, for Intel, things are aweful.

14nm = 909 (= 3.636 nm²) --> which is completely correct (but don't now go to the table and cut off everything to the right of 14nm, because remember the formula will still skew things up)
10nm = 542 (= 2.168 nm²) --> 1.68x (which is completely wrong because Intel will shrink by about 2.00x, about the same as 14nm, so it's not even close)
7nm = 322 (= 1.288 nm²) --> 1.68x (again 1.68x, you can clearly see that these numbers were just invented out of thin air; but it are lies, because when Intel does a shrink, it is around 2x, they take their time for a real full node shrink)

So, these are the raw numbers that were put in the formula. The thing that comes out of the formula, however, has gone through that horrible 0.67 numbers, which makes TSMC's bigger scaling that was put as raw number look even better -- the number that comes out for TSMC, the number you see in the table is both favored by the data that was put in, and by the formula.

So basically, what is done here is that someone used a formula that's already mathematically wrong to put in their secret numbers that are in favor of TSMC, so they can make a reliable looking table with that and claim that this is how things will be, while in fact it could not have been more wrong.

This is the ultimate misleading of course, if you fudge the data and make sure it's almost impossible to find out unless you have someone with some knowledge who decides that it might not be a bad idea to reverse engineer the stuff...

But in your post before you say Tsmc 7nm (0.027µm²) > Intel 10 nm (0.0272µm²). So even you predict Tsmc take leadership in 2018.

TSMC has only disclosed 2 significant figures: the 2 and the 7. It could be anywhere from 0.0265µm² to 0.0274µm².

If you have even a little bit of knowledge of mathematics and rounding, you should see that my Intel estimate (still an estimate based on 22->24) rounds to the same 0.027µm². And in any case, those 2 numbers are within 0.8% of each other, so using anything but the = sign is crazy.

a

What does this 'a' mean?

 

[carop]

If SRAM size will be basically the same, you wouldn't expect major differences, would you? I don't in any case.

Historically, scaling the metal interconnect has been the most challenging aspect of a node shrink. Yes, the metal pitch size tells a lot not only about logic density but also about the difficulty of the node.

Furthermore, the fin pitch is tied to the choice of metal pitch to provide enough fin granularity in logic because the designers always like to have the freedom to pick the number of fins for each transistor based on the drive current requirement.

And remember; there is a lower limit to the number of metal tracks per logic cell and the industry is very close to that. Even though Intel is continuing to play the smaller number of cell tracks game in its N10 technology, SAQP will catch up with them in their N7 technology ;-).

 

[oak8292]

TSMC is willing to make products when yield is ~10%. Intel likes yields to be at least 75%.

Yes TSMC is willing to make products when yields are ~10%, that is what it means to be a foundry.

However on any give contract there is a yield threshold for TSMC to receive full price for the wafer. If my memory is correct with Nvidia there was a shared cost for wafers during the initial ramp to yield and Nvidia was unhappy with how long it took to ramp at 28nm. The die yield is a shared responsibility between the customer and TSMC as it can be an issue with either process or layout. There may even be some shared responsibility with an EDA company. TSMC can not re-spin a design to improve parametric yields. Many of the mobile products being produced at TSMC are a single SKU and not binned and also need to meet a tight time schedule which affects reported yields. So yes TSMC sells wafers at lower yields than Intel.

TSMC has been talking about their yields recently in the last TSMC Open Innovation Platform conference and I will speculate that the really high wafer volume customers like Apple and Qualcomm probably get similar yields very similar to Intel. Intel will need to figure this out if they are going to provide foundry services. Intel typically takes a yield hit when they put out the second generation on a process, e.g. Haswell or Skylake. Yields are going to be more difficult for low volume products.

 

[oak8292]

Woah! This is a Failure since this is their high density cell! Let me explain.

Any thoughts on how Intel and TSMC are using their SRAM cells and whether they have the same design point on performance?

In Bill Holts presentation for transistor density he showed Broadwell and Skylake were using about 10% die area for SRAM and 11% for Reg. Files where as the Apple processors was using around 30% of the die area for SRAM. Is the Intel SRAM to slow for higher level cache? The Apple processor runs a slower frequencies but seems to be using SRAM for all of their cache and also has about twice as much cache.

Could the foundry SRAM be more general purpose?

 

[GilmaSusan]

Is that this regarding SRAM density, logic density, or even each?
Thank in advance

 

[witeken]

Any thoughts on how Intel and TSMC are using their SRAM cells and whether they have the same design point on performance?

In Bill Holts presentation for transistor density he showed Broadwell and Skylake were using about 10% die area for SRAM and 11% for Reg. Files where as the Apple processors was using around 30% of the die area for SRAM. Is the Intel SRAM to slow for higher level cache? The Apple processor runs a slower frequencies but seems to be using SRAM for all of their cache and also has about twice as much cache.

Could the foundry SRAM be more general purpose?

No, it's just that the things that Apple puts on their chip need more SRAM, apparently.

SRAM is high performance memory; there's no alternative AFAIK. You just use as much as you need.

 

[oak8292]

No, it's just that the things that Apple puts on their chip need more SRAM, apparently.

SRAM is high performance memory; there's no alternative AFAIK. You just use as much as you need.

Actually Reg. Files are typically faster and used for L1 Cache and SRAM are used for L2 and L3 Cache. Did Intel miss where Apple was using Reg. Files for L1 or are they saying that Apple doesn't have L1 cache?

Bill did a lot of simplifying as has been done here. The SRAM cell size is being used as a proxy just like the pitches and it seems like it is really over simplifying a lot of engineering design decisions. Actually TSMC 16FFLL includes three different densities of both Reg. Files and SRAM cells for High Density, Ultra High Density and High Speed with one or two ports. Obviously the complexity of analysis goes way way up unless you just simplify to make your point.

Here is some information from ARM on Registers. It includes TSMC 16FFLL, Samsung LPP and Samsung LPE

'High Speed memories for speed critical designs and suitable for L1 cache applications'

http://www.arm.com/products/physical-ip/embedded-memory-ip/register-files.php

ARM SRAM

'Available in 1-Port and 2-Port versions ARM SRAM memory IP typically finds usage in L2/L3 cache solutions, temporary buffers or wherever larger memory instances are required in an SoC design.'

http://www.arm.com/products/physical-ip/embedded-memory-ip/sram.php

The node names may not be 'accurate' if there is anything in a name other than marketing but the availability of tools and information to work with the foundries is exceptional and there is no conflict of interest. TSMC and GF are working to for their customers because that is how they sell wafers.

 

[jpiniero]

TSMCs 10nm was to be a late 2015/2016 product too. 16FF was a 2014 product. 20nm a 2012 product.

I am sure you can see the common denominator.

You compare foundry roadmap to a product roadmap.

True, but it's a big problem for Intel if there are products using TSMC 7FF released in 2018. Especially if it's going to be so close to Intel's 10nm in density. Seems like pretty close to a slam dunk that TSMC should be able to keep Apple in the fold.

 

[Arachnotronic]

Actually Reg. Files are typically faster and used for L1 Cache and SRAM are used for L2 and L3 Cache. Did Intel miss where Apple was using Reg. Files for L1 or are they saying that Apple doesn't have L1 cache?

Bill did a lot of simplifying as has been done here. The SRAM cell size is being used as a proxy just like the pitches and it seems like it is really over simplifying a lot of engineering design decisions. Actually TSMC 16FFLL includes three different densities of both Reg. Files and SRAM cells for High Density, Ultra High Density and High Speed with one or two ports. Obviously the complexity of analysis goes way way up unless you just simplify to make your point.

Here is some information from ARM on Registers. It includes TSMC 16FFLL, Samsung LPP and Samsung LPE

'High Speed memories for speed critical designs and suitable for L1 cache applications'

http://www.arm.com/products/physical-ip/embedded-memory-ip/register-files.php

ARM SRAM

'Available in 1-Port and 2-Port versions ARM SRAM memory IP typically finds usage in L2/L3 cache solutions, temporary buffers or wherever larger memory instances are required in an SoC design.'

http://www.arm.com/products/physical-ip/embedded-memory-ip/sram.php

The node names may not be 'accurate' if there is anything in a name other than marketing but the availability of tools and information to work with the foundries is exceptional and there is no conflict of interest. TSMC and GF are working to for their customers because that is how they sell wafers.

Register files are made up of SRAM cells.

 

[raghu78]

Absolutely wrong, @Arachnotronic . GloFo's 7nm will be a real foundry 7nm node, with its fin pitch of 30nm. It should be very comparable to Intel's 10nm.

http://www.extremetech.com/computin...t-process-full-node-shrink#comment-2900604658

They have time to market gap, sure, but they will really skip the foundry 10nm node.

We'll see if the IBM purchase will result in anything. Of course I've been saying for years that there will be consolidation, so I'm not paying any serious attention to GloFo, but they do what they can with their resources... I guess .

GF 7nm will end up very competitive with Intel 10nm and TSMC 7nm. The process is basically IBM 7nm tech. btw the fin pitch is down in the 30nm range and not exactly 30nm. I would say low 30s is a possibility.

http://www.eetimes.com/document.asp?doc_id=1330467

http://arstechnica.co.uk/gadgets/2015/07/ibm-unveils-industrys-first-7nm-chip-moving-beyond-silicon/

The process will be in production in late 2018, delivering fin pitches "getting down into the 30nm range," initially using only today’s optical lithography.

Some of the key details are - 17 metal layers, 80-84 mask steps, self aligned quadruple patterning on critical layers, silicon germanium alloy channel, EUV compatible. I would expect first AMD products using GF 7 nm in H1 2019. TSMC 7nm will be around 9-12 months ahead of GF 7nm in time to market. But we should have a good comparison of these processes by 2019. Both of them will be competitive with Intel 10nm. This is a high performance process which is going to drive IBM Power CPU and AMD CPU/GPU/APUs.

 

[Arachnotronic]

GF 7nm will end up very competitive with Intel 10nm and TSMC 7nm. The process is basically IBM 7nm tech. btw the fin pitch is down in the 30nm range and not exactly 30nm. I would say low 30s is a possibility.

http://www.eetimes.com/document.asp?doc_id=1330467

http://arstechnica.co.uk/gadgets/2015/07/ibm-unveils-industrys-first-7nm-chip-moving-beyond-silicon/

The process will be in production in late 2018, delivering fin pitches "getting down into the 30nm range," initially using only today’s optical lithography.

Some of the key details are - 17 metal layers, 80-84 mask steps, self aligned quadruple patterning on critical layers, silicon germanium alloy channel, EUV compatible. I would expect first AMD products using GF 7 nm in H1 2019. TSMC 7nm will be around 9-12 months ahead of GF 7nm in time to market. But we should have a good comparison of these processes by 2019. Both of them will be competitive with Intel 10nm. This is a high performance process which is going to drive IBM Power CPU and AMD CPU/GPU/APUs.

You have a lot of faith in GloFo. And, I suppose IBM, too. IBM's 14nm process hasn't even been used to produce a single commercially available product (if it's so great, why didn't GloFo license IBM's instead of Samsung's 14nm process?), and already you're talking about how GloFo's (IBM's) 7nm will be super competitive with Intel and TSMC -- two companies that have much, much better track records than GloFo or IBM.

 

[raghu78]

You have a lot of faith in GloFo. And, I suppose IBM, too. IBM's 14nm process hasn't even been used to produce a single commercially available product (if it's so great, why didn't GloFo license IBM's instead of Samsung's 14nm process?), and already you're talking about how GloFo's (IBM's) 7nm will be super competitive with Intel and TSMC -- two companies that have much, much better track records than GloFo or IBM.

I think IBM's process tech has always been very competitive with Intel. Its just that IBM's CPU manufacturing volume was not enough to sustain their fab business. IBM's tech with GF's volume manufacturing capacity should be a good combination. TSMC has no track record of creating high performance process and products like IBM has done. TSMC has shown they are very good with mobile. You have also said TSMC cannot match Intel in high performance. TSMC 7nm is the first time when they have a high performance process version which will provide 15% higher transistor performance than standard 7nm version which would be mobile optimized. I am looking forward to see how TSMC 7nm HP , GF 7nm HP and Intel 10nm fare and the face off between CPUs from Intel 10nm and AMD built at GF 7nm in 2019.

 

[Arachnotronic]

I think IBM's process tech has always been very competitive with Intel. Its just that IBM's CPU manufacturing volume was not enough to sustain their fab business. IBM's tech with GF's volume manufacturing capacity should be a good combination. TSMC has no track record of creating high performance process and products like IBM has done. TSMC has shown they are very good with mobile. You have also said TSMC cannot match Intel in high performance. TSMC 7nm is the first time when they have a high performance process version which will provide 15% higher transistor performance than standard 7nm version which would be mobile optimized. I am looking forward to see how TSMC 7nm HP , GF 7nm HP and Intel 10nm fare and the face off between CPUs from Intel 10nm and AMD built at GF 7nm in 2019.

IBM's high performance processes have traditionally been plagued by the fact that they are extremely expensive and yield very poorly.

Ask yourself why GloFo didn't use IBM's 22nm SOI process? Why it didn't license IBM's 14nm SOI high performance process (which hasn't even been used to build anything that anyone can buy yet)?

Anyway, we'll see how it all plays out, but I think it takes an extraordinary amount of optimism to think that GlobalFoundries + IBM will be able to suddenly "match" Intel with a "7nm" process when neither company has yet to put a commercially viable FinFET process into production.

Intel and TSMC dramatically outspend these two companies on R&D, are starting off from a much more successful base, and simply have proven that they can make better use of their resources than GloFo/IBM have ever been able to.

 

[Ajay]

Register files are made up of SRAM cells.

Actually, not exactly.

http://electronics.stackexchange.com/questions/72418/is-the-registry-file-made-from-sram

Register files are generally tiny by comparison. The ARM register file is probably somewhere around 200 bits (128 for the main register file, but some parts of various shadow registers as well). Reducing the physical footprint of each memory bit is far less important than maximizing its speed. At minimum, it should be possible to read two arbitrarily-selected registers while writing a third. It should also be possible to simultaneously read the value of a register and write a new value to that register, with a guarantee that the write operation will not affect the value seen by the simultaneous read. A conventionally-laid-out SRAM will not be able to do those things. Instead, register files are often constructed using discrete flips flops or latches with hard-wired enable or multiplexing logic. Chip designers will likely lay out register files in some sort of tiled arrangement, rather than laying out each bit's circuitry independently, but from a functional standpoint the bits of a register file will be implemented using a lot more circuitry for each bit than would be typical in an SRAM array.

 

[raghu78]

TSMC 10nm ahead of schedule. HVM ramp in Q4 2016. Next gen iPad with 10nm A10X chip. Aggressive 7nm ramp HVM ramp schedule for Q4 2017 to support A11X in Q1 2018.

https://www.semiwiki.com/forum/content/6240-will-tsmc-alone-10nm-7nm.html

TSMC 7nm HP

https://www.semiwiki.com/forum/cont...2016-tsmc-open-innovation-platform-forum.html

a) High Performance Computing platform
The majority of the HPC platform discussion pertained to the 7nm node. Characteristics of device models and tool qualification include:

• FEOL device models need to support VDD overdrive and hyper-overdrive performance boost modes
• BEOL interconnect design rules use wider upper level metals, larger vias
• TSMC is providing an “H360” standard cell foundation IP library
• power-grid construction flows focus on minimizing IR, addressing EM issues
• clock-tree synthesis must meet very low skew requirements
• improved wiring delay optimization will be needed in APR flows
• statistical timing analysis support is required
• statistical EM analysis is required

b) Mobile platform
As with HPC, the focus was on the availability of the 16FFC platform, and the development underway for the upcoming 7nm node. Relative to N10FF, the 7nm mobile platform offering offers improvements of ~15% performance (iso-power), ~35% power (iso-performance), with a gate density improvement of 1.65X.

• TSMC is providing an H240 standard cell dense library, for maximal gate density
• Similar EDA reference flow requirements as the HPC platform

I think TSMC is atleast 1 year ahead (maybe more) than the rest of the foundries at 7nm. TSMC 7nm (ARM server designs) and Intel 10nm high performance server products could face off by late 2018 or early 2019.

 

[Ajay]

So is Semiwiki still consider to be a shill for TSMC or was that debunked?

 

[Phynaz]

So is Semiwiki still consider to be a shill for TSMC or was that debunked?

They are a shill for any foundry that will pay.

 

[Ajay]

They are a shill for any foundry that will pay.

In which case we aught not consider their commentary an data as being exact - rather, more like rumored specs

Heh, IOS emojis.

 

[KTE]

TSMC 10nm ahead of schedule. HVM ramp in Q4 2016. Next gen iPad with 10nm A10X chip. Aggressive 7nm ramp HVM ramp schedule for Q4 2017 to support A11X in Q1 2018.

https://www.semiwiki.com/forum/content/6240-will-tsmc-alone-10nm-7nm.html

TSMC 7nm HP

https://www.semiwiki.com/forum/cont...2016-tsmc-open-innovation-platform-forum.html

a) High Performance Computing platform
The majority of the HPC platform discussion pertained to the 7nm node. Characteristics of device models and tool qualification include:

• FEOL device models need to support VDD overdrive and hyper-overdrive performance boost modes
• BEOL interconnect design rules use wider upper level metals, larger vias
• TSMC is providing an “H360” standard cell foundation IP library
• power-grid construction flows focus on minimizing IR, addressing EM issues
• clock-tree synthesis must meet very low skew requirements
• improved wiring delay optimization will be needed in APR flows
• statistical timing analysis support is required
• statistical EM analysis is required

b) Mobile platform
As with HPC, the focus was on the availability of the 16FFC platform, and the development underway for the upcoming 7nm node. Relative to N10FF, the 7nm mobile platform offering offers improvements of ~15% performance (iso-power), ~35% power (iso-performance), with a gate density improvement of 1.65X.

• TSMC is providing an H240 standard cell dense library, for maximal gate density
• Similar EDA reference flow requirements as the HPC platform

I think TSMC is atleast 1 year ahead (maybe more) than the rest of the foundries at 7nm. TSMC 7nm (ARM server designs) and Intel 10nm high performance server products could face off by late 2018 or early 2019.

How is TSMC HVM 7nm/10nm even possible without EUV, which is barely figured out as a cost effective yet?

Sent from HTC 10
(Opinions are own)

 

[jpiniero]

How is TSMC HVM 7nm/10nm even possible without EUV, which is barely figured out as a cost effective yet?

Sent from HTC 10
(Opinions are own)

Intel isn't using EUV at 10 nm.

 

[Ajay]

How is TSMC HVM 7nm/10nm even possible without EUV, which is barely figured out as a cost effective yet?

Sent from HTC 10
(Opinions are own)

Triple and Quad patterning with really expensive computational derived masks. Quad patterning is already used on NAND.
https://en.wikipedia.org/wiki/Multiple_patterning

 

[stingerman]

I think by now it's clear, the node name each foundry uses is decided by marketing not engineering. With that said, what's the performance characteristics and implications. Consider this, the actual processor cores take very little space on the SoC even using 16FFC. The elephant in the room is the logic board and replacing the substrate with wafer level integration is far more of a story than going to 7nm. So, my only interest in 10nm and 7nm would be the the performance/power ratio improvements at each node, not the actual density.

I'd like to see a chart comparing that between each foundry's node.

 

[Arachnotronic]

I think by now it's clear, the node name each foundry uses is decided by marketing not engineering. With that said, what's the performance characteristics and implications. Consider this, the actual processor cores take very little space on the SoC even using 16FFC. The elephant in the room is the logic board and replacing the substrate with wafer level integration is far more of a story than going to 7nm. So, my only interest in 10nm and 7nm would be the the performance/power ratio improvements at each node, not the actual density.

I'd like to see a chart comparing that between each foundry's node.

From what I have heard from people who would know, TSMC's 16FF+ has superior electrical performance to Samsung 14LPP. Intel's 14nm is ahead of both of them and Intel's 14nm+ should extend that lead (which is now obvious from the fin images published of the various processes).

 

[witeken]

(which is now obvious from the fin images published of the various processes).

Are there 14nm+ transistor pictures ?

 

[witeken]

TSMC planning 5nm in 2019 -- so I have to update my sig. But by how much will they shrink if it's only 2 years after 7nm? TSMC and Intel have opposite strategies. Intel does >2x every 3 years, TSMC has switched to doing lesser shrinks faster, probably to give Apple a 1-2 yearly update. At least if they don't lose Apple to Intel. I still won't write off the Intel foundry possibility, even though we've talked about that since 2014.

http://www.eetimes.com/document.asp?doc_id=1330621&

So while Intel is only delaying things, TSMC is pulling in things.