- Dec 25, 2013
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Moore's Law Slowing? Don't Tell TSMChttp://community.cadence.com/cadenc.../archive/2016/03/25/tsmc-manufacturing-status
Well worth a read. I wonder how Intel compares for comparison...
Here some forward looking statements. As always, take with big grain of salt because no one can predict yield learning.
Well, we'll see.
Well worth a read. I wonder how Intel compares for comparison...
TSMC is a manufacturing powerhouse. It has twice the capacity of any other non-memory semiconductor company. It has the best yield in the industry, driven by collecting over 1M datapoints per second from the equipment in its fabs. They are the only company that can ramp from a standing start to full volume by adding 20K wafers per month for three consecutive months. So from 0 to 60K wafers per month in a single quarter (basically manufacturing 90K wafers in the first quarter and then 180K wafers each quarter after that).
20nm was an unprecedentedly steep ramp. However, 16nm was even faster, just three months to full capacity. In 2016, the plans are to continue the N16 ramp to 300,000 wafers per quarter. The defect measure D0 is now a record low <0.06. Was 0.1 when production started. The ramp for N10 is planned to be slightly steeper still.
Here some forward looking statements. As always, take with big grain of salt because no one can predict yield learning.
* 16FFC started ramping this quarter and so should be at 60,000 wafer per month by the end of Q2 or earlier (since the ramps only seem to get faster)
* 10FF starts ramping in 2H 2016 with a planned capacity of 200K wafers/quarter. Risk production is just about to start.
* 7FF qual is planned for Q1 2017 (two processes, high performance and mobile). Risk production March 2017. Ramp in Q2 or Q3.
Two years later they will be at 7nm with a huge density advantage and either a big performance increase for the HP flavor of N7, or a huge power reduction for the mobile version of N7. If all goes to plan, that is something that has never been seen before.
Well, we'll see.