TSMC Shows Path to 16nm, Beyond

[Fjodor2001]

http://www.tomshardware.com/news/tsmc-20-nm-lithography-hkmg,24487.html

Also, more comprehensive info here (but requires login to read more than two articles per day):

http://www.eetimes.com/document.asp?doc_id=1319679

A report from DigiTimes indicates that TSMC has been busy lately with acquiring equipment and preparing to cross over to 20 nm lithography. According to the report, the company will be making the switch in Q1 2014. Shipments for the 16 nm HKMG process have also started, and the company expects mass production of FinFETs to commence about a year from now.

So is Intel's process technology lead shrinking?

 

[Arachnotronic]

http://www.tomshardware.com/news/tsmc-20-nm-lithography-hkmg,24487.html

Also, more comprehensive info here (but requires login to read more than two articles per day):

http://www.eetimes.com/document.asp?doc_id=1319679
So is Intel's process technology lead shrinking?

No, because:

1. TSMC's "16nm" is a 16nm FEOL + 20nm BEOL, so they don't get the logic density improvements by moving to a true "14/16nm" BEOL that Intel will get.

2. What will the yields/cost per wafer look like? It's easy to make a few wafers for the FPGA guys who will be selling the dies for $1k+/pop, but for cheap SoCs, you need really good yields.

The bottom line is that Intel is shipping hundreds of millions of FinFETs today and TSMC is still just talking about it for Q2/Q3 2015. Intel will be launching its own 14nm products in Q3 2014 ("Cherry Trail", "Denverton", and "Broadwell"), which means it's "going into production" (in foundry parlance) in Q4 2013.

The lead is not shrinking.

 

[Phynaz]

Digitimes is wrong as usual. TSMC isn't shipping 16nm, they expect to release the design rules before the end of the year. That means at least three years before a shipping product.

Just stick to the eetimes article.

BTW, TSMC's 16nm isn't a node shrink. It's 20nm FinFET.

 

[Arachnotronic]

Digitimes is wrong as usual. TSMC isn't shipping 16nm, they expect to release the design rules before the end of the year. That means at least three years before a shipping product.

Somebody who gets it

 

[beginner99]

So is Intel's process technology lead shrinking?

It's getting bigger by the minute. TSMC is still at 28 nm and by the time they will have 20 nm, intel will be at 14 nm.

If we are lucky we will see 20 nm GPUs at end of 2014, but it would not surprise me at all if it will be 2015...

 

[ShintaiDK]

Yep, Intels lead keep expanding. Seems TSMC is almost 4 years after Intel now in average technology metric.

I always love these foundry roadmaps vs Intels actual products. I mean TSMC "Shipped" 28nm since 2010....true story...*cough*

 

[erunion]

So is Intel's process technology lead shrinking?

Process technology lead is intact. Roadmap technology lead is shrinking fast!

 

[Fjodor2001]

Well, at least TSMC's chip sales value is impressive:

http://focustaiwan.tw/news/aeco/201310030020.aspx

Taiwan Semiconductor Manufacturing Co. (TSMC) has become the world's largest integrated circuit (IC) chip supplier in terms of the final market value of its sales, the company's acting spokeswoman said Thursday.

Counting the final market value, TSMC's IC chip sales reached an estimated US$54.6 billion last year, TSMC acting spokeswoman Elizabeth Sun said at a media event at the company's flagship production complex in the Southern Taiwan Science Park.

The sales figure surpassed those of IDM (integrated device manufacturer) giants such as U.S.-based Intel Corp. and Samsung Electronics Co. of South Korea, Sun said.

 

[Phynaz]

Well, at least TSMC's chip sales value is impressive:

http://focustaiwan.tw/news/aeco/201310030020.aspx

Already discredited.
http://forums.anandtech.com/showthread.php?t=2344229

 

[kevinsbane]

Well, at least TSMC's chip sales value is impressive:

http://focustaiwan.tw/news/aeco/201310030020.aspx

Yes, but here's the important bit:

Counting the final market value, TSMC's IC chip sales reached an estimated US$54.6 billion last year, TSMC acting spokeswoman Elizabeth Sun said at a media event at the company's flagship production complex in the Southern Taiwan Science Park.

Final market value. Not revenue. So, basically, this isn't TSMC's sales... it's the sales of products that TSMC chips go into. It's like saying that Intel's revenue = the total cost of every computer, laptop, chipset and service that Intel chips go into. It's a meaningless number, one trotted out by that acting spokesperson.

 

[Gikaseixas]

Given the market state, high margins route is the wrong one. Selling high volumes/low margins is the way and that's why TSMC is gaining some traction here but Intel is changing and starting to focus on the real prize. To me 2013 is a odd year, 2014-2015 will see Intel extend it's lead.

 

[Exophase]

Digitimes is wrong as usual. TSMC isn't shipping 16nm, they expect to release the design rules before the end of the year. That means at least three years before a shipping product.

Just stick to the eetimes article.

BTW, TSMC's 16nm isn't a node shrink. It's 20nm FinFET.

OP is too optimistic but you're too pessimistic, basically saying 2017 for the first shipping TSMC 16nm product. You do know they taped out a Cortex-A57 test chip on 16nm months ago, right? While that doesn't reflect a real product it's a good indicator of what the state of risk production is like, I don't think it's really going to be 3 years until a product. I think you're taking that comment of "allow to design" to mean something it doesn't. If you look at later pages in the article you'll see TSMC anticipates several tape-outs on 16nm in 1H 2014. It's not uncommon for tapeout to release of real products to take about a year. So some releases by end of 2015 seems reasonable to me. Late 2016 or early 2017 isn't really fair.

 

[Phynaz]

If you look at later pages in the article you'll see TSMC anticipates several tape-outs on 16nm in 1H 2014.

Does the article state if those *anticipated* tape-outs customer sell-able products, or test chips?

Remember, this is the same company that is touting themselves as being the larger semiconductor manufacturer in the world, based upon a made up metric.

TSMC has taped out several 20nm chips and expects to let customers start designing 16nm FinFET chips before the end of the year. By the end of 2014 it expects it will have taped out 25 20nm designs and be far along in work on 30 16nm chips.

I see no mention of 16nm tape-out.

 

[Exophase]

Does the article state if those *anticipated* tape-outs customer sell-able products, or test chips?

Remember, this is the same company that is touting themselves as being the larger semiconductor manufacturer in the world, based upon a made up metric.

It doesn't say, but given that there's already been a tape out of a test product of decent complexity, I doubt it. Why would they promote taping out several test chips? It doesn't gel with the rest of the context of the article, including the tapeout projections for 20nm (but more to the point, I don't think it's in TSMC's interests to publicize such a thing, the only reason the A57 tapeout even got the press release it did was because it was done in conjunction with another party)

Is it really that surprising that the transition from TSMC's 20nm to 16nm could be faster than previous transitions precisely because they're using the same BEOL? They wouldn't be doing things this way if they weren't determined to get out a stepping stone product to get things moving faster.

Seriously, if you're going to tell people "stick with the EE times article" at least read beyond the first couple paragraphs. I know you have to register for the site and all but it's not that bad Like I said, I don't think you're interpreting "start designing" the way TSMC means you to, and even if that's true I've never seen a rule of thumb that it's 3 years from having the design rules to production.

 

[Khato]

Given the market state, high margins route is the wrong one. Selling high volumes/low margins is the way and that's why TSMC is gaining some traction here but Intel is changing and starting to focus on the real prize. To me 2013 is a odd year, 2014-2015 will see Intel extend it's lead.

Exactly. At this point I'm rather convinced that a good part of the reason for Otellini's decision to retire is that he didn't see a good high-margin strategy for Intel going forward... whereas all evidence thus far is that BK intends to use Intel's manufacturing advantage to its full effect and take the resulting hit on gross margins. Which, in my opinion, is unquestionably the correct move to take for the exact same reasons as the last time that Intel was in in an 'architecture war' back in the 80's/90's. Namely, so long as they're making adequate profits to maintain the business model then they want to sell every chip they possibly can not to make money so much as to deprive their competition of the sale.

Intel is arguably in a far stronger position now than they were then. Not only do they have an indisputable lead in process technology but Samsung is the only competitor that's an IDM, which is important when it comes to the question of 'how low can you go?'

Coming back 'round to TSMC, the tidbits available regarding their '16nm' FF process certainly make it sound promising - it may well still be competitive whenever it shows up. So long as they deliver what they've indicated, it should outperform Intel's 22nm... unfortunately we have pretty much no idea what to expect of Intel's 14nm despite first products supposedly being less than a year away. But even if their process technology is competitive it's still a perilous time for TSMC. They've been investing heavily in expansion for anticipated future demand, but if Intel undercuts their customers then they suddenly have the very real possibility of leading edge fabs sitting idle. (That depriving the competition of sales by perfectly legitimate means is an extremely effective tactic in an industry with such high fixed costs.)

 

[Phynaz]

Why would they promote taping out several test chips?

Marketing. Just like when Intel announced FinFET and the next day IBM/AMD announced they had it too.
Or this one from TSMC in April:

TSMC pulled in plans for initial production of its 16-nm FinFET process to the end of 2013.

Seems either a lot changed in less than six months or TSMC is full of stuff. Such as calling a test chip "production" - which would be technically correct because they did produce it - but it isn't in the spirit of what people think of as production.

Seriously, if you're going to tell people "stick with the EE times article" at least read beyond the first couple paragraphs. I know you have to register for the site and all but it's not that bad Like I said, I don't think you're interpreting "start designing" the way TSMC means you to, and even if that's true I've never seen a rule of thumb that it's 3 years from having the design rules to production.

I've been registered with EETimes for a decade...Before they were even called EETimes.

Rule of thumb for chip design is four years for a complex product (CPU/GPU). Cutting off the first year - assuming the functional design is complete - gives you three years.

 

[Idontcare]

Process technology lead is intact. Roadmap technology lead is shrinking fast!

This is the size of it.

TSMC is making strides towards Finfet, make no bones about it. But they are nowhere close to a production ready process flow at this time. Yields are abysmal and the lifetime reliability is in the crapper.

One of the big hurdles in finfet production is implementing a robust means of capturing, quantifying, and leveraging the non-uniformity and variability of dopants, fin width, fin height, and LER (line edge roughness) in a production environment.

You can't just put billions of finfets on a 1cm^2 area of silicon and expect them all to be the same, the addition of the 3rd dimension enables an order of magnitude more complexity in the entropy domain. And entropy always means process variation and transistor variation.

TSMC is still in the early stages of figuring out how they are going to effectively manage that new degree of freedom in the production environment.

They'll get there eventually, but oh boy I sure don't want to be the one buying the first finfet chips coming out of TSMC. Not until they really get there heads wrapped around the process variability problem, and right now they are drowning in it.

 

[CHADBOGA]

Already discredited.
http://forums.anandtech.com/showthread.php?t=2344229

Fjodor2001 keeps hitting them out of the park. :biggrin:

 

[Exophase]

Marketing. Just like when Intel announced FinFET and the next day IBM/AMD announced they had it too.

Or this one from TSMC in April:

Seems either a lot changed in less than six months or TSMC is full of stuff. Such as calling a test chip "production" - which would be technically correct because they did produce it - but it isn't in the spirit of what people think of as production.

You sound like you're picking and choosing what makes things look as pessimistic as possible and discarding anything else. You're saying that despite a complete Cortex-A57 taping out in April no one else can start any process-specific work until the end of the year.

You're seriously reaching if you think that all 12 of the tapeouts they refer to in 1H 2014 are going to be like the A57 one already reported. At any rate, I was wrong, they DO refer to it specifically as "product tapeouts" in the slide. They do refer to it as adoption (how could internal test chips be considered adoption?) It's clearly meant to show customer involvement with the process. And I get the feeling that giving a specific count like this is derived from schedules of real products in development and not just projection.

In one instance they're reported as saying that they'll start producing 16nm at the end of the year. In another instance it's that they'll let people start designing 16nm at the end of the year. Maybe they're not really saying such different things, but the reporter is interpreting and presenting them differently.

Rule of thumb for chip design is four years for a complex product (CPU/GPU). Cutting off the first year - assuming the functional design is complete - gives you three years.

Four years I'll take, but the part about one year to complete the functional design (including all pre-physical validation) then three years for physical implementation sounds pretty hand wavey.

 

[Phynaz]

Four years I'll take, but the part about one year to complete the functional design (including all pre-physical validation) then three years for physical implementation sounds pretty hand wavey.

One year functional design.
Two years physical design and layout.
One year validation.

 

[Abwx]

Two years physical design and layout.

With old school methods but not with semi automated design....

 

[Khato]

You're saying that despite a complete Cortex-A57 taping out in April no one else can start any process-specific work until the end of the year.

Why not? Last I checked the eventual result of a tapeout can be anything from a fully functional piece of silicon to a very small electrical space heater, no?

 

[Exophase]

Why not? Last I checked the eventual result of a tapeout can be anything from a fully functional piece of silicon to a very small electrical space heater, no?

Since when was it something you could do with zero capability to design anything for the process?

 

[carop]

1. TSMC's "16nm" is a 16nm FEOL + 20nm BEOL, so they don't get the logic density improvements by moving to a true "14/16nm" BEOL that Intel will get.

Do you know the process details for Intel and foundries at 16nm/14nm? If so, would you care to share them?

I am talking about Architecture, Routing, Contacted poly pitch, Metal pitch, Local interconnect, Strain engineering, Double patterning etc.

Thanks.

 

[Fjodor2001]

Fjodor2001 keeps hitting them out of the park. :biggrin:

Maybe you should ask yourself what you have brought to this discussion except flaming?