ShintaiDK
Lifer
- Apr 22, 2012
- 20,378
- 145
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I'm certain there is a way to interleave 2 1GB stacks into a single 1024-bit channel, memory has always by its very nature been interleaved. This "dual link interposer" business is totally made up as far as I can tell... unless y'all are trying to talk about merely interleaved memory on the same bus.
The Anandtech write up even explicitly called out that it should be easier to incorporate control logic now that its all on an interposer. GPU would see a 2GB memory pool on that 1024-bit bus, control chip could split it across the two attached stacks (much like PLX bridges for PCIe for example). It's for sure possible.
Now whether AMD actually did this or not is an entirely different issue. The slide seem to imply they designed for 4 GB. It could be that an interleaved design ruins the latency advantage of HBM or any other variety of issues they identified with such a solution. I trust that there would be a reason, even if its just that going to 8 with an interleaved design adds too much cost.
The way is to double the stack height
HBM2 will double the stack height from 4 to 8. But also increase the densities from 2Gbit to 8Gbit.
It may simply have been AMD or Hynix being too optimistic what they could deliver in the timeframe. Hynix itself have been overly optimistic because they dreamt of 8 high HBM1 and 16 high HBM2. That has been reduced to half later on in their precentations. A classic issue of new untested technology and manufactoring.
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